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rev. 4383b?8051?01/05 features 80c51 core architecture 256 bytes of on-chip ram 2048 bytes of on-chip eram 64k bytes of on-chip flash memory ? data retention: 10 years at 85c ? read/write cycle: 100k boot code section with independent lock bits 2k bytes of on-chip flash for bootloader in-system programming by on-chip uart boot program and iap capability 2k bytes of on-chip eeprom read/write cycle: 100k integrated power monitor (por: pfd) to supervise internal power supply 14-sources 4-level interrupts three 16-bit timers/counters full duplex uart compatible 80c51 high-speed architecture ? in standard mode: 40 mhz (vcc 3v to 5.5v, both internal and external code execution) 60 mhz (vcc 4.5v to 5.5v and internal code execution only) ? in x2 mode (6 clocks/machine cycle) 20 mhz (vcc 3v to 5.5v, both internal and external code execution) 30 mhz (vcc 4.5v to 5.5v and internal code execution only) five ports: 32 + 4 digital i/o lines five-channel 16-bit pca with ? pwm (8-bit) ? high-speed output ? timer and edge capture double data pointer 21-bit watchdog timer (7 programmable bits) a 10-bit resolution analog to digital converter (adc) with 8 multiplexed inputs spi interface (plcc52 and vpfp64 packages only) on-chip emulation logic (enhanced hook system) power saving modes ?idle mode ? power-down mode power supply: 3 volts to 5.5 volts temperature range: industrial (-40 to +85 c) packages: vqfp44, plcc44, vqfp64, plcc52 description the AT89C51AC3 is a high performance flash version of the 80c51 single chip 8-bit microcontrollers. in x2 mode a maximum external clock rate of 20 mhz reaches a 300 ns cycle time. besides the AT89C51AC3 provides 64k bytes of flash memory including in-system programming (isp) and iap, 2k bytes boot flash memory, 2k bytes eeprom and 2048 byte eram. primary attention is paid to the reduction of the electro-magnetic emission of AT89C51AC3. enhanced 8-bit microcontroller with 64kb flash memory AT89C51AC3
2 AT89C51AC3 4383b?8051?01/05 block diagram notes: 1. 8 analog inputs/8 digital i/o 2. 5-bit i/o port timer 0 int ram 256x8 t0 t1 rxd txd wr rd ea psen ale xtal2 xtal1 uart cpu timer 1 int1 ctrl int0 c51 core port 0 p0 port 1 port 2 port 3 parallel i/o ports and ext. bus p1 (1) p2 p3 eram 2048 ib-bus pca reset watch dog pca eci vss vcc timer2 t2ex t2 port 4 p4 (2) emul unit 10 bit adc flash 64k x 8 boot loader 2kx8 ee prom 2kx8 spi interface mosi sck miso
3 AT89C51AC3 4383b?8051?01/05 pin configuration plcc44 p1.3/an3/cex0 p1.2/an2/eci p1.1/an1/t2ex p1.0/an 0/t2 varef vagnd reset vss vcc xtal1 xtal2 p3.7/rd p4.0 p4.1 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p3.6/wr 39 38 37 36 35 34 33 32 29 30 31 7 8 9 10 11 12 13 14 17 16 15 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 44 43 42 41 40 ale psen p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.1/ad1 p0.0/ad0 p2.0/a8 p1.4/an4/cex1 p1.5/an5/cex2 p1.6/an6/cex3 p1.7/an7/cex4 ea p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 1 43 42 41 40 39 44 38 37 36 35 34 12 13 17 16 15 14 20 19 18 21 22 33 32 31 30 29 28 27 26 25 24 23 vqfp44 1 2 3 4 5 6 7 8 9 10 11 p1.4/an4/cex1 p1.5/an5/cex2 p1.6/an6/cex3 p1.7/an7/cex4 ea p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 ale psen p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.2 /ad2 p0.3 /ad3 p0.4 /ad4 p0.1 /ad1 p0.0 /ad0 p2.0/a8 p1.3/an3/cex0 p1.2/an2/eci p1.1/an1/t2ex p1.0/an 0/t2 varef vagnd reset vss vcc xtal1 xtal2 p3.7/rd p4.0 p4.1 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p3.6/wr
4 AT89C51AC3 4383b?8051?01/05 21 22 26 25 24 23 29 28 27 30 31 5 4 3 2 1 6 52 51 50 49 48 8 9 10 11 12 13 14 15 16 17 18 46 45 44 43 42 41 40 39 38 37 36 plcc52 7 47 19 20 32 33 34 35 p1.3/an3/cex0 p1.2/an2/eci p1.1/an1/t2ex p1.0/an 0/t2 varef vagnd reset vss vcc xtal1 xtal2 testi p1.4/an4/cex1 p1.5/an5/cex2 p1.6/an6/cex3 p1.7/an7/cex4 ea p3.0/rxd p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/ss p4.3/sck ale psen p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.2 /ad2 p0.3 /ad3 p0.4 /ad4 p0.1 /ad1 p0.0 /ad0 p2.0/a8 p4.4/mosi p3.7/rd p4.0 p4.1 p2.7/a15 p2.6/a14 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p3.6/wr p4.2/miso nc nc nc testi must be connected to vss vcc 54 53 52 51 50 49 vqfp64 p1.3/an3/cex 0 p1.2/an2/eci p1.1/an1/t2e x p1.0/an0/t2 varef vagnd reset vss vss vss p3.7/rd p4.0 p4.1 p2.7/a15 p2.6/a14 nc nc nc nc p3.6/wr 48 47 46 45 44 43 42 41 39 40 1 2 3 4 5 6 7 8 10 9 17 18 19 20 21 22 23 24 25 26 64 63 62 61 60 59 58 57 56 55 nc ale psen p0.7/ad7 p0.6/ad6 nc p0.5/ad5 nc nc p0.4/ad4 p1.4/an4/cex1 nc p1.5/an5/cex2 p1.6/an6/cex3 p1.7/an7/cex4 nc ea nc nc p3.0/rxd 11 12 13 16 15 14 p4.3/sck p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/ss 38 37 36 33 34 35 p0.1/ad1 p0.2/ad2 p0.3/ad3 p4.4/mosi p0.0/ad0 p2.0/a8 p2.5/a13 p2.4/a12 p2.3/a11 p2.2/a10 p2.1/a9 p4.2/miso 27 28 29 30 31 32 testi vcc vcc xtal1 xtal2 vcc testi must be connected to vss
5 AT89C51AC3 4383b?8051?01/05 pin name type description vss gnd circuit ground testi i must be connected to vss vcc supply voltage varef reference voltage for adc vagnd reference ground for adc p0.0:7 i/o port 0: is an 8-bit open drain bi-directional i/o port. port 0 pins that have 1?s written to them float, and in this state can be used as high-impedance inputs. port 0 is also the multiplexed low-or der address and data bus during accesses to external program and data memory. in this application it uses strong internal pull-ups when emitting 1?s. port 0 also outputs the code bytes during program validation. external pull-ups are required during program verification. p1.0:7 i/o port 1: is an 8-bit bi-directional i/o port with internal pull-ups. po rt 1 pins can be used for digital input/output or as analog input s for the analog digital converter (adc). port 1 pins that have 1?s wr itten to them are pulled high by the internal pull-up transisto rs and can be used as inputs in this state. as inputs, port 1 pi ns that are being pulled low externally will be the source of curr ent (i il , see section "electrical characteristic") because of the in ternal pull-ups. port 1 pins are assigned to be used as analog inputs via the adccf register (in this case the internal pull-ups are disconnected). as a secondary digital function, port 1 contains the timer 2 ex ternal trigger and clock input; the pca external clock input and the pca module i/o. p1.0/an0/t2 analog input channel 0, external clock input for timer/counter2. p1.1/an1/t2ex analog input channel 1, trigger input for timer/counter2. p1.2/an2/eci analog input channel 2, pca external clock input. p1.3/an3/cex0 analog input channel 3, pca module 0 entry of input/pwm output. p1.4/an4/cex1 analog input channel 4, pca module 1 entry of input/pwm output. p1.5/an5/cex2 analog input channel 5, pca module 2 entry of input/pwm output. p1.6/an6/cex3 analog input channel 6, pca module 3 entry of input/pwm output. p1.7/an7/cex4 analog input channel 7, pca module 4 entry ot input/pwm output. port 1 receives the low-order address byte dur ing eprom programming and program verification. it can drive cmos inputs without external pull-ups. p2.0:7 i/o port 2: is an 8-bit bi-directional i/o port with internal pull-ups. port 2 pins that have 1?s written to them are pulled high by the in ternal pull-ups and can be used as inputs in this state. as inputs, port 2 pins that are being pulled lo w externally will be a source of current (i il , see section "electrical characteristic ") because of the internal pull-ups. po rt 2 emits the high-order address byte during accesses to the external program memory and during acce sses to external data memo ry that uses 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when emitting 1?s. during accesses to external data memory that use 8 bit addresses (movx @ri), port 2 transmi ts the contents of the p2 special function register. it also receives high-order addresses and control signals during program validation. it can drive cmos inputs without external pull-ups.
6 AT89C51AC3 4383b?8051?01/05 p3.0:7 i/o port 3: is an 8-bit bi-directional i/o port with internal pull-ups. port 3 pins that have 1?s written to them are pulled high by the in ternal pull-up transistors and can be used as inputs in this state. as inputs, port 3 pins that are being pulled low externally will b e a source of current (i il , see section "electrical characteristic ") because of the internal pull-ups. the output latch corresponding to a secondary function must be programmed to one for that function to operate (except for txd and wr ). the secondary functions are assigned to the pins of port 3 as follows: p3.0/rxd: receiver data input (asynchronous) or data input /output (synchronous) of the serial interface p3.1/txd: transmitter data output (asynchronous) or clock out put (synchronous) of the serial interface p3.2/int0 : external interrupt 0 input/timer 0 gate control input p3.3/int1 : external interrupt 1 input/timer 1 gate control input p3.4/t0: timer 0 counter input p3.5/t1/ss : timer 1 counter input spi slave select p3.6/wr : external data memory write strobe; latches the data byte from port 0 into the external data memory p3.7/rd : external data memory read strobe; enables the external data memory. it can drive cmos inputs without external pull-ups. p4.0:4 i/o port 4: is an 2-bit bi-directional i/o port with internal pull-ups. port 4 pins that have 1?s written to them are pulled high by the in ternal pull-ups and can be used as inputs in this state. as inputs, port 4 pins that are being pulled lo w externally will be a source of current (iil, on the datasheet) because of the internal pull-up transistor. the secondary functions are assigned to the 5 pins of port 4 as follows: p4.0: regular port i/o p4.1: regular port i/o p4.2/miso: master input slave output of spi controller p4.3/sck: serial clock of spi controller p4.4/mosi: master ouput slave input of spi controller it can drive cmos inputs without external pull-ups. pin name type description
7 AT89C51AC3 4383b?8051?01/05 i/o configurations each port sfr operates via type-d latches, as illustrated in figure 1 for ports 3 and 4. a cpu "write to latch" signal initiates transfer of internal bus data into the type-d latch. a cpu "read latch" signal transfers the latched q output onto the internal bus. similarly, a "read pin" signal transfers the logical level of the port pin. some port data instructions activate the "read latch" signal while others activate the "read pin" signal. latch instruc- tions are referred to as read-modify-write instructions. each i/o line may be independently programmed as input or output. port 1, port 3 and port 4 figure 1 shows the structure of ports 1 and 3, which have internal pull-ups. an external source can pull the pin low. each port pin can be configured either for general-purpose i/o or for its alternate input output function. to use a pin for general-purpose output, set or clear the corresponding bit in the px reg- ister (x = 1,3 or 4). to use a pin for general-purpose input, set the bit in the px register. this turns off the output fet drive. to configure a pin for its alternate function, set the bit in the px register. when the latch is set, the "alternate output function" signal controls the output level (see figure 1). the operation of ports 1, 3 and 4 is discussed further in the "quasi-bidirectional port opera- tion" section. reset i/o reset: a high level on this pin during two machine cycles while the osci llator is running resets the dev ice. an internal pull-down resistor to vss permits power-on reset using only an external capacitor to vcc. ale o ale: an address latch enable output for latching the low byte of t he address during accesses to the external memory. the ale is activated every 1/6 oscillator periods (1/3 in x2 mode) exc ept during an external data memory access. when instructions are executed from an internal flash (ea = 1), ale generation can be disabled by the software. psen o psen : the program store enable output is a control signal that enables the external program memory of the bus during external fetch operations. it is activated twice each machine cycle duri ng fetches from the external program memory. however, when executing from of the external program me mory two activations of psen are skipped during each access to the external data memory. the psen is not activated for internal fetches. ea i ea : when external access is held at the high level, instructions are fetched from the internal flash. when held at the low level, AT89C51AC3 fetches all instructions from the external program memory . xtal1 i xtal1: input of the in verting oscillator amplifier and input of the internal clock generator circuits. to drive the device from an external clock source, xtal1 should be driven, while xtal2 is left unconnected. to operate above a frequency of 16 mhz, a duty cycle of 50% should be maintained. xtal2 o xtal2: output from the inverting oscillator amplifier. pin name type description
8 AT89C51AC3 4383b?8051?01/05 figure 1. port 1, port 3 and port 4 structure note: the internal pull-up can be disabled on p1 when analog function is selected. port 0 and port 2 ports 0 and 2 are used for general-purpose i/o or as the external address/data bus. port 0, shown in figure 3, differs from the other ports in not having internal pull-ups. figure 3 shows the structure of port 2. an external source can pull a port 2 pin low. to use a pin for general-purpose output, set or clear the corresponding bit in the px reg- ister (x = 0 or 2). to use a pin for general-purpose input, set the bit in the px register to turn off the output driver fet. figure 2. port 0 structure notes: 1. port 0 is precluded from use as general-purpose i/o ports when used as address/data bus drivers. 2. port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. except for these bus cycles, the pull-up fet is off, port 0 outputs are open-drain. d cl q p1.x latch internal write to latch read pin read latch p1. x p3.x p4.x alternate output function vcc internal pull-up (1) alternate input function p3. x p4. x bus d q p0.x latch internal write to latch read pin read latch 0 1 p0.x (1 ) address low/ data control vdd bus (2)
9 AT89C51AC3 4383b?8051?01/05 figure 3. port 2 structure notes: 1. port 2 is precluded from use as general-purpose i/o ports when as address/data bus drivers. 2. port 2 internal strong pull-ups fet (p1 in figure) assist the logic-one output for memory bus cycle. when port 0 and port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line. read-modify-write instructions some instructions read the latch data rather than the pin data. the latch based instruc- tions read the data, modify the data and then rewrite the latch. these are called "read- modify-write" instructions. below is a comple te list of these special instructions (see table ). when the destination operand is a port or a port bit, these instructions read the latch rather than the pin: it is not obvious the last three instructions in this list are read-modify-write instructions. these instructions read the port (all 8 bits), modify the specifically addressed bit and d q p2.x latch internal write to latch read pin read latch 0 1 p2.x (1) address high/ control bus vdd internal pull-up (2) instruction description example anl logical and anl p1, a orl logical or orl p2, a xrl logical ex-or xrl p3, a jbc jump if bit = 1 and clear bit jbc p1.1, label cpl complement bit cpl p3.0 inc increment inc p2 dec decrement dec p2 djnz decrement and jump if not zero djnz p3, label mov px.y, c move carry bit to bit y of port x mov p1.5, c clr px.y clear bit y of port x clr p2.4 set px.y set bit y of port x set p3.3
10 AT89C51AC3 4383b?8051?01/05 write the new byte back to the latch. these read-modify-write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. for example, a port bit used to drive the base of an external bipolar transistor can not rise above the transistor?s base-emitter junction voltage (a value lower than vil). with a logic one written to the bit, attempts by the cpu to read the port at the pin are misinterpreted as logic zero. a read of the latch rather than the pins returns the correct logic-one value. quasi-bidirectional port operation port 1, port 2, port 3 and port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" ports. when configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. port 0 is a "true bidirectional" pin. the pins float when configured as input. resets write logic one to all port latches. if logical zero is subsequently written to a port latch, it can be returned to input conditions by a logical one written to the latch. note: port latch values change near the end of read-modify-write instruction cycles. output buffers (and therefore the pin state) update early in the instruction after read-modify- write instruction cycle. logical zero-to-one transitions in port 1, port 2, port 3 and port 4 use an additional pull- up (p1) to aid this logic transition (see figure 4.). this increases switch speed. this extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. the internal pull-ups are field-effect transistors rather than linear resistors. pull- ups consist of three p-channel fet (pfet) devices. a pfet is on when the gate senses logical zero and off when the gate senses logical one. pfet #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the port latch. a logical one at the port pin turns on pfet #3 (a weak pull-up) through the inverter. this inverter and pfet pair form a latch to drive logical one. pfet #2 is a very weak pull-up switched on whenever the associated nfet is switched off. this is traditional cmos switch con- vention. current strengths are 1/10 that of pfet #3. figure 4. internal pull-up configurations note: port 2 p1 assists the logic-one output for memory bus cycles. read pin input data p1. x output data 2 osc. periods n p1(1) p2 p3 vcc vcc vcc p2. x p3. x p4. x
11 AT89C51AC3 4383b?8051?01/05 sfr mapping the special function registers (sfrs) of the AT89C51AC3 fall into the following categories: mnemonicaddname 76543210 acce0haccumulator ???????? b f0hb register ???????? psw d0h program status word cy ac f0 rs1 rs0 ov f1 p sp81hstack pointer ???????? dpl 82h data pointer low byte lsb of dptr ???????? dph 83h data pointer high byte msb of dptr ???????? mnemonicaddname 76543210 p080hport 0 ???????? p190hport 1 ???????? p2a0hport 2 ???????? p3b0hport 3 ???????? p4 c0h port 4 (x5) ? ? ? p4.4 / mosi p4.3 / sck p4.2 / miso p4.1 p4.0 mnemonicaddname 76543210 th0 8ch timer/counter 0 high byte ???????? tl0 8ah timer/counter 0 low byte ???????? th1 8dh timer/counter 1 high byte ???????? tl1 8bh timer/counter 1 low byte ???????? th2 cdh timer/counter 2 high byte ???????? tl2 cch timer/counter 2 low byte ???????? tcon 88h timer/counter 0 and 1 control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tmod 89h timer/counter 0 and 1 modes gate1 c/t1# m11 m01 gate0 c/t0# m10 m00
12 AT89C51AC3 4383b?8051?01/05 t2con c8h timer/counter 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# t2mod c9h timer/counter 2 mode ??????t2oedcen rcap2h cbh timer/counter 2 reload/capture high byte ???????? rcap2l cah timer/counter 2 reload/capture low byte ???????? wdtrst a6h watchdog timer reset ???????? wdtprg a7h watchdog timer program ?????s2s1s0 mnemonicaddname 76543210 mnemonicaddname 76543210 scon 98h serial control fe/sm0 sm1 sm2 ren tb8 rb8 ti ri sbuf99hserial data buffer???????? saden b9h slave address mask ? ? ? ? ? ? ? ? saddra9hslave address ???????? mnemonic addname 76543210 ccon d8h pca timer/counter control cf cr ? ccf4 ccf3 ccf2 ccf1 ccf0 cmod d9h pca timer/counter mode cidl wdte ? ? ? cps1 cps0 ecf cl e9h pca timer/counter low byte ???????? ch f9h pca timer/counter high byte ???????? ccapm0 ccapm1 ccapm2 ccapm3 ccapm4 dah dbh dch ddh deh pca timer/counter mode 0 pca timer/counter mode 1 pca timer/counter mode 2 pca timer/counter mode 3 pca timer/counter mode 4 ? ecom0 ecom1 ecom2 ecom3 ecom4 capp0 capp1 capp2 capp3 capp4 capn0 capn1 capn2 capn3 capn4 mat0 mat1 mat2 mat3 mat4 tog0 tog1 tog2 tog3 tog4 pwm0 pwm1 pwm2 pwm3 pwm4 eccf0 eccf1 eccf2 eccf3 eccf4 ccap0h ccap1h ccap2h ccap3h ccap4h fah fbh fch fdh feh pca compare capture module 0 h pca compare capture module 1 h pca compare capture module 2 h pca compare capture module 3 h pca compare capture module 4 h ccap0h7 ccap1h7 ccap2h7 ccap3h7 ccap4h7 ccap0h6 ccap1h6 ccap2h6 ccap3h6 ccap4h6 ccap0h5 ccap1h5 ccap2h5 ccap3h5 ccap4h5 ccap0h4 ccap1h4 ccap2h4 ccap3h4 ccap4h4 ccap0h3 ccap1h3 ccap2h3 ccap3h3 ccap4h3 ccap0h2 ccap1h2 ccap2h2 ccap3h2 ccap4h2 ccap0h1 ccap1h1 ccap2h1 ccap3h1 ccap4h1 ccap0h0 ccap1h0 ccap2h0 ccap3h0 ccap4h0 ccap0l ccap1l ccap2l ccap3l ccap4l eah ebh ech edh eeh pca compare capture module 0 l pca compare capture module 1 l pca compare capture module 2 l pca compare capture module 3 l pca compare capture module 4 l ccap0l7 ccap1l7 ccap2l7 ccap3l7 ccap4l7 ccap0l6 ccap1l6 ccap2l6 ccap3l6 ccap4l6 ccap0l5 ccap1l5 ccap2l5 ccap3l5 ccap4l5 ccap0l4 ccap1l4 ccap2l4 ccap3l4 ccap4l4 ccap0l3 ccap1l3 ccap2l3 ccap3l3 ccap4l3 ccap0l2 ccap1l2 ccap2l2 ccap3l2 ccap4l2 ccap0l1 ccap1l1 ccap2l1 ccap3l1 ccap4l1 ccap0l0 ccap1l0 ccap2l0 ccap3l0 ccap4l0
13 AT89C51AC3 4383b?8051?01/05 mnemonicaddname 76543210 ien0 a8h interrupt enable control 0 ea ec et2 es et1 ex1 et0 ex0 ien1 e8h interrupt enable control 1 ????espi?eadc? ipl0 b8h interrupt priority control low 0 ? ppc pt2 ps pt1 px1 pt0 px0 iph0 b7h interrupt priority control high 0 ? ppch pt2h psh pt1h px1h pt0h px0h ipl1 f8h interrupt priority control low 1 ? ? ? ?spil?padcl? iph1 f7h interrupt priority control high1 ????spih?padch? mnemonicaddname 76543210 adcon f3h adc control ? psidle aden adeoc adsst sch2 sch1 sch0 adcf f6h adc configuration ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 adclk f2h adc clock ? ? ? prs4 prs3 prs2 prs1 prs0 addh f5h adc data high byte adat9 adat8 adat7 adat6 adat5 adat4 adat3 adat2 addl f4h adc data low byte ? ? ? ? ? ? adat1 adat0 mnemonicaddname 76543210 spcon d4h spi control spr2 spen ssdis mstr cpol cpha spr1 spr0 spscr d5h spi status and control spif ? ovr modf spte uartm spteie mofie spdatd6hspi data ???????? mnemonicaddname 76543210 pcon 87h power control smod1 smod0 ? pof gf1 gf0 pd idl auxr 8eh auxiliary register 0 dpu vpfdp m0 xrs2 xrs1 xrs0 extram a0 auxr1 a2h auxiliary register 1 ? ? enboot ? gf3 0 ? dps ckcon0 8fh clock control 0 ? wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 ckcon1 9fh clock control 1 ? ? ? ? ? ? ? spix2 fcon d1h flash control fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy eecon d2h eeprom contol eepl3 eepl2 eepl1 eepl0 ? ? eee eebusy fsta d3 flash status - - - - - - seqerr fload
14 AT89C51AC3 4383b?8051?01/05 reserved note: 1. do not read or write reserved registers 2. these registers are bit ? addressable. sixteen addresses in the sfr space are both byte ? addressable and bit ? addressable. the bit ? addressable sfr?s are those whose address ends in 0 and 8. the bit addresses, in this area, are 0x80 through to 0xff. table 1. sfr mapping 0/8 (2) 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ipl1 xxxx x0x0 ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 ffh f0h b 0000 0000 adclk xxx0 0000 adcon x000 0000 addl 0000 0000 addh 0000 0000 adcf 0000 0000 iph1 xxxx x0x0 f7h e8h ien1 xxxx x0x0 cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 efh e0h acc 0000 0000 e7h d8h ccon 0000 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 dfh d0h psw 0000 0000 fcon 0000 0000 eecon xxxx xx00 fsta xxxx xx00 spcon 0001 0100 spscr 0000 0000 spdat xxxx xxxx d7h c8h t2con 0000 0000 t2mod xxxx xx00 rcap2l 0000 0000 rcap2h 0000 0000 tl2 0000 0000 th2 0000 0000 cfh c0h p4 xxx1 1111 c7h b8h ipl0 x000 0000 saden 0000 0000 bfh b0h p3 1111 1111 iph0 x000 0000 b7h a8h ien0 0000 0000 saddr 0000 0000 afh a0h p2 1111 1111 auxr1 xxxx 00x0 wdtrst 1111 1111 wdtprg xxxx x000 a7h 98h scon 0000 0000 sbuf 0000 0000 ckcon1 xxxx xxx0 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 auxr x001 0100 ckcon0 x00 0000 8fh 80h p0 1111 1111 sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon 00x1 0000 87h 0/8 (2) 1/9 2/a 3/b 4/c 5/d 6/e 7/f
15 AT89C51AC3 4383b?8051?01/05 clock the AT89C51AC3 core needs only 6 clock periods per machine cycle. this feature, called?x2?, provides the following advantages: divides frequency crystals by 2 (cheaper crystals) while keeping the same cpu power. saves power consumption while keeping the same cpu power (oscillator power saving). saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. increases cpu power by 2 while keeping the same crystal frequency. in order to keep the original c51 compatibility, a divider-by-2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by the software. an extra feature is available to start after reset in the x2 mode. this feature can be enabled by a bit x2b in the hardware security byte. this bit is described in the section "in-system programming". description the x2 bit in the ckcon register (see table 2) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit activates the x2 feature (x2 mode) for the cpu clock only (see figure 5.). the timers 0, 1 and 2, uart, pca or watchdog switch in x2 mode only if the corre- sponding bit is cleared in the ckcon register. the clock for the whole circuit and peripheral is first divided by two before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on the xtal1 input. in x2 mode, as this divider is bypassed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 5. shows the clock generation block diagram. the x2 bit is validated on the xtal1 2 rising edge to avoid glitches when switching from the x2 to the std mode. figure 6 shows the mode switching waveforms.
16 AT89C51AC3 4383b?8051?01/05 figure 5. clock cpu generation diagram x tal1 x tal2 pd pcon.1 cpu core 1 0 2 periph clock clock peripheral cpu clock cpu core clock symbol x2 ckcon.0 x2b hardware byte wdx2 ckcon0.6 pcax2 ckcon0.5 six2 ckcon0.4 t2x2 ckcon0.3 t1x2 ckcon0.2 t0x2 ckcon0.1 idl pcon.0 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 x2 ckcon.0 fwd clock fpca clock fuart clock ft2 clock ft1 clock ft0 clock and adc on reset 1 0 2 fspiclock spix2 ckcon1.0 clock symbol
17 AT89C51AC3 4383b?8051?01/05 figure 6. mode switching waveforms note: in order to prevent any incorrect operation while operating in the x2 mode, users must be aware that all peripherals using the clock frequency as a time reference (uart, timers...) will have their time reference divided by two. for example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. a uart with a 4800 baud rate will have a 9600 baud rate. xtal2 cpu x2 bit x2 mode std mode std mode
18 AT89C51AC3 4383b?8051?01/05 registers table 2. ckcon0 register ckcon0 (s:8fh) clock control register note: 1. this control bit is validated when the cpu clock bit x2 is set; when x2 is low, this bit has no effect. reset value = x000 0000b 76543210 - wdx2 pcax2 six2 t2x2 t1x2 t0x2 x2 bit number bit mnemonic description 7- reserved the value read from this bits is indeterminate. do not set this bit. 6wdx2 watchdog clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 5pcax2 programmable counter array clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4six2 enhanced uart clo ck (mode 0 and 2) (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 3t2x2 timer2 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 2t1x2 timer1 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 1t0x2 timer0 clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6 clock periods per machine cycle (x2 mode) and to enable the individual peripherals "x2"bits.
19 AT89C51AC3 4383b?8051?01/05 table 3. ckcon1 register ckcon1 (s:9fh) clock control register 1 note: 1. this control bit is validated when the cpu clock bit x2 is set; when x2 is low, this bit has no effect. reset value = xxxx xxx0b 76543210 spix2 bit number bit mnemonic description 7-1 - reserved the value read from these bits is indeterminate. do not set these bits. 0 spix2 spi clock (1) clear to select 6 clock periods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle.
20 AT89C51AC3 4383b?8051?01/05 data memory the AT89C51AC3 provides data memory access in two different spaces: 1. the internal space mapped in three separate segments: the lower 128 bytes ram segment. the upper 128 bytes ram segment. the expanded 2048 bytes ram segment (eram). 2. the external space. a fourth internal segment is available but dedicated to special function registers, sfrs, (addresses 80h to ffh ) accessible by direct addressing mode. figure 8 shows the internal and external data memory spaces organization. figure 7. internal memory - ram figure 8. internal and external data memory organization eram-xram upper 128 bytes internal ram lower 128 bytes internal ram special function registers 80h 80h 00h ffh ffh direct addressing addressing 7fh direct or indirect indirect addressing 256 up to 2048 bytes 00h 64k bytes external xram 0000h ffffh internal eram extram = 0 extram = 1 ffh or 7ffh internal external
21 AT89C51AC3 4383b?8051?01/05 internal space lower 128 bytes ram the lower 128 bytes of ram (see figure 8) are accessible from address 00h to 7fh using direct or indirect addressing modes. the lowest 32 bytes are grouped into 4 banks of 8 registers (r0 to r7). two bits rs0 and rs1 in psw register (see figure 6) select which bank is in use according to table 4. this allows more efficient use of code space, since register instructions are shorte r than instructions that use direct address- ing, and can be used for context switching in interrupt service routines. table 4. register bank selection the next 16 bytes above the register banks form a block of bit-addressable memory space. the c51 instruction set includes a wi de selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. the bit addresses in this area are 00h to 7fh. figure 9. lower 128 bytes internal ram organization upper 128 bytes ram the upper 128 bytes of ram are accessible from address 80h to ffh using only indirect addressing mode. expanded ram the on-chip 2048 bytes of expanded ram (eram) are accessible from address 0000h to 07ffh using indirect addressing mode through movx instructions. in this address range, the bit extram in auxr register is used to select the eram (default) or the xram. as shown in figure 8 when extram = 0, the eram is selected and when extram = 1, the xram is selected. the size of eram can be configured by xrs2-0 bit in auxr register (default size is 2048 bytes). note: lower 128 bytes ram, upper 128 bytes ram, and expanded ram are made of volatile memory cells. this means that the ram content is indeterminate after power-up and must then be initialized properly. rs1 rs0 description 0 0 register bank 0 from 00h to 07h 0 1 register bank 0 from 08h to 0fh 1 0 register bank 0 from 10h to 17h 1 1 register bank 0 from 18h to 1fh bit-addressable space 4 banks of 8 registers r0-r7 30h 7fh (bit addresses 0-7fh) 20h 2fh 18h 1fh 10h 17h 08h 0fh 00h 07h
22 AT89C51AC3 4383b?8051?01/05 external space memory interface the external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (rd#, wr#, and ale). figure 10 shows the structure of the external address bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed with a7:0 on p0. table 5 describes the external memory interface signals. figure 10. external data memory interface structure table 5. external data memory interface signals external bus cycles this section describes the bus cycles the AT89C51AC3 executes to read (see figure 11), and write data (see figure 12) in the external data memory. external memory cycle takes 6 cpu clock periods. this is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in x2 mode. for further infor- mation on x2 mode. slow peripherals can be accessed by stretching the read and write cycles. this is done using the m0 bit in auxr register. setting this bit changes the width of the rd# and wr# signals from 3 to 15 cpu clock periods. for simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing in formation. for bus cycle timing parameters refer to the section ?ac characteristics? of the AT89C51AC3 datasheet. signal name type description alternative function a15:8 o address lines upper address lines for the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals indicates that valid address information are available on lines ad7:0. - rd# o read read signal output to external data memory. p3.7 wr# o write write signal output to external memory. p3.6 ram peripheral AT89C51AC3 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale wr oe rd# wr# latch
23 AT89C51AC3 4383b?8051?01/05 figure 11. external data read waveforms notes: 1. rd# signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. figure 12. external data write waveforms notes: 1. wr# signal may be stretched using m0 bit in auxr register. 2. when executing movx @ri instruction, p2 outputs sfr content. ale p0 p2 rd#1 dpl or ri d7:0 dph or p22 p2 cpu clock ale p0 p2 wr#1 dpl or ri d7:0 p2 cpu clock dph or p22
24 AT89C51AC3 4383b?8051?01/05 dual data pointer description the AT89C51AC3 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. dptr 0 and dptr 1 are seen by the cpu as dptr and are accessed using the sfr addresses 83h and 84h that are the dph and dpl addresses. the dps bit in auxr1 register (see figure 8) is used to select whether dptr is the data pointer 0 or the data pointer 1 (see figure 13). figure 13. dual data pointer implementation application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare?) are well served by using one data pointer as a ?source? pointer and the other one as a ?destination? pointer. hereafter is an example of block move implementation using the two pointers and coded in assembler. the latest c compiler takes also advantage of this feature by providing enhanced algorithm libraries. the inc instruction is a short (2 bytes) and fast (6 machine cycle) way to manipulate the dps bit in the auxr1 register. however, note that the inc instruction does not directly force the dps bit to a particular state, but simply toggles it. in simple routines, such as the block move example, only the fact that dps is toggled in the proper sequence mat- ters, not its actual value. in other words, the block move routine works the same whether dps is '0' or '1' on entry. ; ascii block move using dual data pointers ; modifies dptr0, dptr1, a and psw ; ends when encountering null character ; note: dps exits opposite to the entry state unless an extra inc auxr1 is added auxr1equ0a2h move:movdptr,#source ; address of source incauxr1 ; switch data pointers movdptr,#dest ; address of dest mv_loop:incauxr1; switch data pointers movxa,@dptr; get a byte from source incdptr; increment source address incauxr1; switch data pointers movx@dptr,a; write the byte to dest incdptr; increment dest address jnzmv_loop; check for null terminator end_move: 0 1 dph0 dph1 dpl0 0 1 dps auxr1.0 dph dpl dpl1 dptr dptr0 dptr1
25 AT89C51AC3 4383b?8051?01/05 registers table 6. psw register psw (s:8eh) program status word register reset value = 0000 0000b table 7. auxr register auxr (s:8eh) auxiliary register 76543210 cy ac f0 rs1 rs0 ov f1 p bit number bit mnemonic description 7cy carry flag carry out from bit 1 of alu operands. 6ac auxiliary carry flag carry out from bit 1 of addition operands. 5f0 user definable flag 0. 4-3 rs1:0 register bank select bits refer to table 4 for bits description. 2ov overflow flag overflow set by arithmetic operations. 1f1 user definable flag 1 0p parity bit set when acc contains an odd number of 1?s. cleared when acc contains an even number of 1?s. 76543210 - - m0 xrs2 xrs1 xrs0 extram a0 bit number bit mnemonic description 7-6 - reserved the value read from these bits are indeterminate. do not set this bit. 5m0 stretch movx control: the rd/ and the wr/ pulse length is increased according to the value of m0. m0 pulse length in clock period 0 6 1 30
26 AT89C51AC3 4383b?8051?01/05 reset value = x001 0100b not bit addressable table 8. auxr1 register auxr1 (s:a2h) auxiliary control register 1 reset value = xxxx 00x0b 4-2 xrs1-0 eram size: accessible size of the eram xrs 2:0 eram size 000 256 bytes 001 512 bytes 010 768 bytes 011 1024 bytes 100 1792 bytes 101 2048 bytes (default configuration after reset) 110 reserved 111 reserved 1extram internal/external ram (00h - ffh) access using movx @ ri/@ dptr 0 - internal eram access using movx @ ri/@ dptr. 1 - external data memory access. 0a0 disable/enable ale) 0 - ale is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if x2 mode is used) 1 - ale is active only during a movx or movc instruction. 76543210 - - enboot - gf3 0 - dps bit number bit mnemonic description 7-6 - reserved the value read from these bits is indeterminate. do not set these bits. 5 enboot enable boot flash set this bit for map the boot flash between f800h -ffffh clear this bit for disable boot flash. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3gf3 general-purpose flag 3 20 always zero this bit is stuck to logic 0 to allow inc auxr1 instruction without affecting gf3 flag. 1- reserved for data pointer extension. 0dps data pointer select bit set to select second dual data pointer: dptr1. clear to select first dual data pointer: dptr0. bit number bit mnemonic description
27 AT89C51AC3 4383b?8051?01/05 power monitor the por/pfd function monitors the internal power-supply of the cpu core memories and the peripherals, and if needed, suspends their activity when the internal power sup- ply falls below a safety threshold. this is achieved by applying an internal reset to them. by generating the reset the power monitor insures a correct start up when at89c51cc03 is powered up. description in order to startup and maintain the microcontroller in correct operating mode, v cc has to be stabilized in the v cc operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level vih/vil. these parameters are controlled during the three phases: power-up, normal operation and power going down. see figure 14. figure 14. power monitor block diagram note: 1. once xtal1 high and low levels reach above and below vih/vil a 1024 clock period delay will extend the reset coming from the power fail detect. if the power falls below the power fail detect thresthold level, the reset will be applied immediately. the voltage regulator generates a regulated internal supply for the cpu core the mem- ories and the peripherals. spikes on the external vcc are smoothed by the voltage regulator. the power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the figure 15. vcc power on reset power fail detect voltage regulator xtal1 (1) cpu core memories peripherals regulated supply rst pin hardware watchdog pca watchdog internal reset
28 AT89C51AC3 4383b?8051?01/05 figure 15. power fail detect when the power is applied, the power monitor immediately asserts a reset. once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the xtal clock input. the internal reset will remain asserted until the xtal1 lev- els are above and below vih and vil. further more. an internal counter will count 1024 clock periods before the reset is de-asserted. if the internal power supply falls below a safety level, a reset is immediately asserted. . vcc t reset vcc
29 AT89C51AC3 4383b?8051?01/05 reset introduction the reset sources are : power management, hardware watchdog, pca watchdog and reset input. figure 16. reset schematic reset input the reset input can be used to force a reset pulse longer than the internal reset con- trolled by the power monitor. rst input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to v cc as shown in figure 17. resistor value and input characteristics are discussed in the section ?dc characteristics? of the AT89C51AC3 datasheet. the status of the port pins during reset is detailed in table 9. figure 17. reset circuitry and power-on reset power monitor hardware watchdog pca watchdog rst internal reset rst r rst vss to internal reset rst vdd + b. power-on rese t a. rst input circuitry
30 AT89C51AC3 4383b?8051?01/05 reset output as detailed in section ?watchdog timer?, page 79, the wdt generates a 96-clock period pulse on the rst pin. in order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit, a 1 k ? resis- tor must be added as shown figure 18. figure 18. recommended reset output schematic rst vdd + vss vdd rst 1k to other on-board circuitry AT89C51AC3
31 AT89C51AC3 4383b?8051?01/05 power management introduction two power reduction modes are implemented in the AT89C51AC3. the idle mode and the power-down mode. these modes are detailed in the following sections. in addition to these power reduction modes, the clocks of the core and peripherals can be dynami- cally divided by 2 using the x2 mode detailed in section ?clock?, page 15. idle mode idle mode is a power reduction mode that reduces the power consumption. in this mode, program execution halts. idle mode freezes the clock to the cpu at known states while the peripherals continue to be clocked. the cpu status before entering idle mode is preserved, i.e., the program counter and program status word register retain their data for the duration of idle mode. the contents of the sfrs and ram are also retained. the status of the port pins during idle mode is detailed in table 9. entering idle mode to enter idle mode, set the idl bit in pcon register (see table 10). the AT89C51AC3 enters idle mode upon execution of the instruction that sets idl bit. the instruction that sets idl bit is the last instruction executed. note: if idl bit and pd bit are set simultaneously, the AT89C51AC3 enters power-down mode. then it does not go in idle mode when exiting power-down mode. exiting idle mode there are two ways to exit idle mode: 1. generate an enabled interrupt. ? hardware clears idl bit in pcon register which restores the clock to the cpu. execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated idle mode. the general purpose flags (gf1 and gf0 in pcon register) may be used to indicate whether an interrupt occurred during normal operation or during idle mode. when idle mode is exited by an interrupt, the interrupt service routine may examine gf1 and gf0. 2. generate a reset. ? a logic high on the rst pin clears idl bit in pcon register directly and asynchronously. this restores the clock to the cpu. program execution momentarily resumes with the instruction immediately following the instruction that activated the idle mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the AT89C51AC3 and vectors the cpu to address c:0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated idle mode should not write to a port pin or to the external ram. power-down mode the power-down mode places the AT89C51AC3 in a very low power state. power- down mode stops the oscillator, freezes all clock at known states. the cpu status prior to entering power-down mode is preserved, i.e., the program counter, program status word register retain their data for the duration of power-down mode. in addition, the sfr and ram contents are preserved. the status of the port pins during power-down mode is detailed in table 9. note: vcc may be reduced to as low as v ret during power-down mode to further reduce power dissipation. take care, however, that vdd is not reduced until power-down mode is invoked.
32 AT89C51AC3 4383b?8051?01/05 entering power-down mode to enter power-down mode, set pd bit in pcon register. the AT89C51AC3 enters the power-down mode upon execution of the instruction that sets pd bit. the instruction that sets pd bit is the last instruction executed. exiting power-down mode note: if vcc was reduced during the power-down mode, do not exit power-down mode until vcc is restored to the normal operating level. there are two ways to exit the power-down mode: 1. generate an enabled external interrupt. ? the AT89C51AC3 provides capability to exit from power-down using int0#, int1#. hardware clears pd bit in pcon register which starts the oscillator and restores the clocks to the cpu and peripherals. using intx# input, execution resumes when the input is released (see figure 19). execution resumes with the interrupt service routine. upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated power-down mode. note: the external interrupt used to exit power-down mode must be configured as level sensi- tive (int0# and int1#) and must be assigned the highest priority. in addition, the duration of the interrupt must be long enough to allow the oscillator to stabilize. the exe- cution will only resume when the interrupt is deasserted. note: exit from power-down by external interrupt does not affect the sfrs nor the internal ram content. figure 19. power-down exit waveform using int1:0# 2. generate a reset. ? a logic high on the rst pin clears pd bit in pcon register directly and asynchronously. this starts the oscillator and restores the clock to the cpu and peripherals. program execution momentarily resumes with the instruction immediately following the instruction that activated power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. reset initializes the AT89C51AC3 and vectors the cpu to address 0000h. note: during the time that execution resumes, the internal ram cannot be accessed; however, it is possible for the port pins to be accessed. to avoid unexpected outputs at the port pins, the instruction immediately following the instruction that activated the power-down mode should not write to a port pin or to the external ram. note: exit from power-down by reset redefines all the sfrs , but does not affect the internal ram content. int1:0# osc power-down phase oscillator restart phase active phase active phase
33 AT89C51AC3 4383b?8051?01/05 table 9. pin conditions in special operating modes mode port 0 port 1 port 2 port 3 port 4 ale psen# reset floating high high high high high high idle (internal code) data data data data data high high idle (external code) floating data data data data high high power- down(inter nal code) data data data data data low low power- down (external code) floating data data data data low low
34 AT89C51AC3 4383b?8051?01/05 registers table 10. pcon register pcon (s87:h) power configuration register reset value= xxxx 0000b 76543210 ----gf1gf0pd idl bit number bit mnemonic description 7-4 - reserved the value read from these bits is indeterminate. do not set these bits. 3gf1 general purpose flag 1 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 2gf0 general purpose flag 0 one use is to indicate whether an interrupt occurred during normal operation or during idle mode. 1pd power-down mode bit cleared by hardware when an in terrupt or reset occurs. set to activate the power-down mode. if idl and pd are both set, pd takes precedence. 0idl idle mode bit cleared by hardware when an in terrupt or reset occurs. set to activate the idle mode. if idl and pd are both set, pd takes precedence.
35 AT89C51AC3 4383b?8051?01/05 eeprom data memory the 2-kbyte on-chip eeprom memory block is located at addresses 0000h to 07ffh of the xram/eram memory space and is selected by setting control bits in the eecon register. a read in the eeprom memory is done with a movx instruction. a physical write in the eeprom memory is done in two steps: write data in the column latches and transfer of all data latches into an eeprom memory row (programming). the number of data written on the page may vary from 1 up to 128 bytes (the page size). when programming, only the data written in the column latch is programmed and a ninth bit is used to obtain this feature. this provides the capability to program the whole memory by bytes, by page or by a number of bytes in a page. indeed, each ninth bit is set when the writing the corresponding byte in a row and all these ninth bits are reset after the writing of the complete eeprom row. write data in the column latches data is written by byte to the column latches as for an external ram memory. out of the 11 address bits of the data pointer, the 4 msbs are used for page selection (row) and 7 are used for byte selection. between two eeprom programming sessions, all the addresses in the column latches must stay on the same page, meaning that the 4 msb must no be changed. the following procedure is used to write to the column latches: save and disable interrupt. set bit eee of eecon register load dptr with the address to write store a register with the data to be written execute a movx @dptr, a if needed loop the three last instructions until the end of a 128 bytes page restore interrupt. note: the last page address used when loading the column latch is the one used to select the page programming address. programming the eeprom programming consists of the following actions: writing one or more bytes of one page in the column latches. normally, all bytes must belong to the same page; if not, the first page address will be latched and the others discarded. launching programming by writing the control sequence (50h followed by a0h) to the eecon register. eebusy flag in eecon is then set by hardware to indicate that programming is in progress and that the eeprom segment is not available for reading. the end of programming is indicated by a hardware clear of the eebusy flag. note: the sequence 5xh and axh must be executed without instructions between then other- wise the programming is aborted. read data the following procedure is used to read the data stored in the eeprom memory: save and disable interrupt set bit eee of eecon register load dptr with the address to read execute a movx a, @dptr restore interrupt
36 AT89C51AC3 4383b?8051?01/05 examples ;*f*************************************************************************;* name: api_rd_eeprom_byte ;* dptr contain address to read. ;* acc contain the reading value ;* note: before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_rd_eeprom_byte: mov eecon, #02h; map eeprom in xram space movx a, @dptr mov eecon, #00h; unmap eeprom ret ;*f************************************************************************* ;* name: api_ld_eeprom_cl ;* dptr contain address to load ;* acc contain value to load ;* note: in this example we load only 1 byte, but it is possible upto ;* 128 bytes. ;* before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_ld_eeprom_cl: mov eecon, #02h ; map eeprom in xram space movx @dptr, a moveecon, #00h; unmap eeprom ret ;*f************************************************************************* ;* name: api_wr_eeprom ;* note: before execute this function, be sure the eeprom is not busy ;*************************************************************************** api_wr_eeprom: mov eecon, #050h mov eecon, #0a0h ret
37 AT89C51AC3 4383b?8051?01/05 registers table 11. eecon register eecon (s:0d2h) eeprom control register reset value = xxxx xx00b not bit addressable 76543210 eepl3 eepl2 eepl1 eepl0 - - eee eebusy bit number bit mnemonic description 7-4 eepl3-0 programming launch command bits write 5xh followed by axh to eepl to launch the programming. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1eee enable eeprom space bit set to map the eeprom space during movx instructions (write in the column latches) clear to map the xram space during movx. 0eebusy programming busy flag set by hardware when programming is in progress. cleared by hardware when programming is done. can not be set or cleared by software.
38 AT89C51AC3 4383b?8051?01/05 program/code memory the AT89C51AC3 implement 64k bytes of on-chip program/code memory. figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. the flash memory increases eprom and rom functionality by in-circuit electrical era- sure and programming. thanks to the internal charge pump, the high voltage needed for programming or erasing flash cells is gen erated on-chip using the standard vdd volt- age. thus, the flash memory can be programmed using only one voltage and allows in- system programming commonly known as is p. hardware programming mode is also available using specific programming tool. figure 20. program/code memory organization 0000h 64k bytes ffffh internal 0000h ffffh flash 64k bytes external memory ea = 0 ea = 1
39 AT89C51AC3 4383b?8051?01/05 external code memory access memory interface the external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (psen#, and ale). figure 21 shows the structure of the external address bus. p0 carries address a7:0 while p2 carries address a15:8. data d7:0 is multiplexed with a7:0 on p0. table 21 describes the external memory interface signals. figure 21. external code memory interface structure external bus cycles this section describes the bus cycles the AT89C51AC3 executes to fetch code (see figure 22) in the external program/code memory. external memory cycle takes 6 cpu clock periods. this is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in x2 mode. for further infor- mation on x2 mode see section ?clock ?. for simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. for bus cycling parameters refer to the ?ac-dc parameters? section. table 12. external code memory interface signals signal name type description alternate function a15:8 o address lines upper address lines fo r the external bus. p2.7:0 ad7:0 i/o address/data lines multiplexed lower address lines and data for the external memory. p0.7:0 ale o address latch enable ale signals indicates that valid address information are available on lines ad7:0. - psen# o program store enable output this signal is active low during exte rnal code fetch or external code read (movc instruction). - flash eprom AT89C51AC3 p2 p0 ad7:0 a15:8 a7:0 a15:8 d7:0 a7:0 ale latch oe psen#
40 AT89C51AC3 4383b?8051?01/05 figure 22. external code fetch waveforms flash memory architecture AT89C51AC3 features two on-chip flash memories: flash memory fm0: containing 64k bytes of program memory (user space) organized into 128 byte pages, flash memory fm1: 2k bytes for boot loader and application programming interfaces (api). the fm0 can be program by both parallel programming and serial in-system program- ming (isp) whereas fm1 supports only parallel programming by programmers. the isp mode is detailed in the "in-system programming" section. all read/write access operations on flash memory by user application are managed by a set of api described in the "in-system programming" section. the bit enboot in auxr1 register is used to map fm1 from f800h to ffffh. figure 23 and figure 24 show the flash memory configuration with enboot=1 and enboot=0. figure 23. flash memory architecture with enboot=1 (boot mode) ale p0 p2 psen# pcl pch pch pcl d7:0 d7:0 pch d7:0 cpu clock ffffh 64k bytes fm0 0000h hardware security (1 byte) column latches (128 bytes) extra row (128 bytes) 2k bytes flash memory fm1 boot space ffffh f800h fm1 mapped between ffffh and f800h when bit enboot is set in auxr1 register f800h memory space not accessible
41 AT89C51AC3 4383b?8051?01/05 figure 24. flash memory architecture with enboot=0 (user modemode) ffffh 64k bytes fm0 0000h hardware security (1 byte) column latches (128 bytes) extra row (128 bytes) 2k bytes flash memory fm1 boot space ffffh f800h fm1 mapped between ffffh and f800h when bit enboot is set in auxr1 register f800h memory space not accessible
42 AT89C51AC3 4383b?8051?01/05 fm0 memory architecture the flash memory is made up of 4 blocks (see figure 23): the memory array (user space) 64k bytes the extra row the hardware security bits the column latch registers user space this space is composed of a 64k bytes fl ash memory organized in 512 pages of 128 bytes. it contains the user?s application code. extra row (xrow) this row is a part of fm0 and has a size of 128 bytes. the extra row may contain infor- mation for boot loader usage. hardware security byte (hsb) the hardware security byte space is a part of fm0 and has a size of 1 byte. the 4 msb can be read/written by software (from fm0 and , the 4 lsb can only be read by software and written by hardware in parallel mode. h hardware security byte (hsb) column latches the column latches, also part of fm0, have a size of full page (128 bytes). the column latches are the entrance buffers of the three previous memory locations (user array, xrow and hardware security byte). the column latches are write only and can be accessed only from fm1 (boot mode) and from external memory cross flash memory access description the fm0 memory can be program only from fm1. programming fm0 from fm0 or from external memory is impossible. the fm1 memory can be program only by parallel programming. the table show all software flash access allowed. 76543210 x2 bljb - - - lb2 lb1 lb0 bit number bit mnemonic description 7x2 x2 mode programmed (=?0?) to force x2 mode (6 clocks per instruction) after reset unprogrammed to force x1 mode, standard mode, afetr reset (default) 6bljb boot loader jump bit when unprogrammed (=?1?), at the next reset : -enboot=0 (see code space memory configuration) -start address is 0000h (pc=0000h) when programmed (=?0?)at the nex reset: -enboot=1 (see code space memory configuration) -start address is f800h (pc=f800h) 5- reserved 4- reserved 3- reserved 2-0 lb2-0 general memory lock bits (only programmable by programmer tools) section ?flash protection from parallel programming?, page 51
43 AT89C51AC3 4383b?8051?01/05 cross flash memory access (a) depend upon general lock bit configuration. code executing from action fm0 (user flash) fm1 (boot flash) fm0 (user flash) read ok - load column latch ok - write - - fm1 (boot flash) read ok ok load column latch ok - write ok - external memory ea = 0 read (a) - load column latch - - write - -
44 AT89C51AC3 4383b?8051?01/05 overview of fm0 operations flash registers (sfr) the cpu interfaces to the flash memory through the fcon register, auxr1 register and fsta register. these registers are used to map the column latches, hsb, extra row and eedata in the working data or code space. fcon register table 13. fcon register fcon register (s:d1h) flash control register reset value= 0000 0000b 76543210 fpl3 fpl2 fpl1 fpl0 fps fmod1 fmod0 fbusy bit number bit mnemonic description 7-4 fpl3:0 programming launch command bits write 5xh followed by axh to launch the programming according to fmod1:0. (see table 16.) 3fps flash map program space when this bit is set: the movx @dptr, a instruction writes in the columns latches space when this bit is cleared: the movx @dptr, a instruction writes in the regular xdata memory space 2-1 fmod1:0 flash mode see table 16. 0fbusy flash busy set by hardware when progr amming is in progress. clear by hardware w hen programming is done. can not be changed by software.
45 AT89C51AC3 4383b?8051?01/05 fsta register table 14. fsta register fsta register (s:d3h) flash status register reset value= 0000 0000b mapping of the memory space by default, the user space is accessed by movc a, @dptr instruction for read only. the column latches space is made accessible by setting the fps bit in fcon register. writing is possible from 0000h to ffffh, address bits 6 to 0 are used to select an address within a page while bits 15 to 7 are used to select the programming address of the page. setting fps bit takes precedence on the extram bit in auxr register. the other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits fmod0 and fmod1 in fcon register in accor- dance with table 15. a movc instruction is then used for reading these spaces. table 15. fm0 blocks select bits notes: 1. the column latches reset is a new option introduced in the AT89C51AC3, and is not available in t89c51cc01/2 launching programming fpl3:0 bits in fcon register are used to secure the launch of programming. a specific sequence must be written in these bits to unlock the write protection and to launch the programming. this sequence is 5xh followed by axh. table 16 summarizes the memory spaces to program according to fmod1:0 bits. 76543210 seqerr fload bit number bit mnemonic description 7-2 unusesd 1seqerr flash activation sequence error set by hardware when the flash acti vation sequence(mov fcon 5x and mov fcon ax )is not correct (see error repport section) clear by software or clear by hardwar e if the last activation sequence was correct (previous error are canceled) 0fload flash colums latch loaded set by hardware when the first data is loaded in the column latches. clear by hardware when the activation s equence suceed (flash write sucess, or reset column latch success) fmod1 fmod0 fm0 adressable space 0 0 user (0000h-ffffh) 0 1 extra row(ff80h-ffffh) 1 0 hardware security byte (0000h) 1 1 column latches reset (note1)
46 AT89C51AC3 4383b?8051?01/05 table 16. programming spaces notes: 1. the sequence 5xh and axh must be executing without instructions between them otherwise the programming is not executed (see flash status register) 2. the sequence 5xh and axh must be executed with the same fmod0 fmod1 configuration. 3. interrupts that may occur during programming time must be disabled to avoid any spurious exit of the programming mode. status of the flash memory the bit fbusy in fcon register is used to indicate the status of programming. fbusy is set when programming is in progress. the flash programming process is launched the second machine cycle following the sequence 5xh and axh in fcon. thus the fbusy flag should be read by sofware not during the insctruction after the 5xh, axh sequence but the the second instruction after the 5xh, axh sequence in fcon (see next example). fbusy is cleared when the pro- gramming is completed. ;*f************************************************************************* ;* name: launch_prog ;;*************************************************************************** launch_prog: mov fcon, #050h mov fcon #0a0h ; flash write sequence nop ;required time before reading busy flag wait_busy: mov a,fcon jb acc.0,wait_busy ret selecting fm1 the bit enboot in auxr1 register is used to map fm1 from f800h to ffffh. loading the column latches any number of data from 1-byte to 128 bytes can be loaded in the column latches. this provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. data written in the column latches do not have to be in consecutive write to fcon operation fpl3:0 fps fmod1 fmod0 user 5 x 0 0 no action ax0 0 write the column latches in user space extra row 5 x 0 1 no action ax0 1 write the column latches in extra row space hardware security byte 5 x 1 0 no action a x 1 0 write the fuse bits space reset columns latches 5 x 1 1 no action a x 1 1 reset the column latches
47 AT89C51AC3 4383b?8051?01/05 order. the page address of the last addre ss loaded in the column latches will be used for the whole page. when programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, then programming is effectively done. thus no page or block erase is needed and only the loaded data are programmed in the corresponding page notes: 1. : if no bytes are written in the column latches the seqerr bit in the fsta register will be set. 2. when a flash write sequence is in progress (fbusy is set) a write sequence to the column latches will be ignored and the content of the column latches at the time of the launch write sequence will be preserved. 3. movx @dptr, a instruction must be used to load the column latches. never use movx @ri, a instructions. 4. when a programming sequence is launched, flash bytes corresponding to activated bytes in the column latches are first erased then the bytes in the column latches are copied into the flash bytes. flash bytes corresponding to bytes in the column latches not activated (not loaded during the load column latches sequence) will not be erased and written. the following procedure is used to load the column latches and is summarized in figure 25: save and disable interrupt and map the column latch space by setting fps bit. load the dptr with the address to load. load accumulator register with the data to load. execute the movx @dptr, a instruction. if needed loop the three last instructions until the page is completely loaded. unmap the column latch. restore interrupt
48 AT89C51AC3 4383b?8051?01/05 figure 25. column latches loading procedure note: the last page address used when loading the column latch is the one used to select the page programming address. programming the flash spaces user the following procedure is used to prog ram the user space and is summarized in figure 26: load up to one page of data in the co lumn latches from address 0000h to ffffh. save and disable the interrupts. launch the programming by writing the data sequence 50h followed by a0h in fcon register (only from fm1). the end of the programming indicated by the fbusy flag cleared. restore the interrupts. extra row the following procedure is used to program the extra row space and is summarized in figure 26: load data in the column latches from address ff80h to ffffh. save and disable the interrupts. launch the programming by writing the data sequence 52h followed by a2h in fcon register (only from fm1). the end of the programming indicated by the fbusy flag cleared. restore the interrupts. column latches loading data load dptr = address acc = data exec: movx @dptr, a last byte to load? column latches mapping fcon = 08h (fps=1) data memory mapping fcon = 00h (fps = 0) save and disable it ea = 0 restore it
49 AT89C51AC3 4383b?8051?01/05 figure 26. flash and extra row programming procedure hardware security byte the following procedure is used to program the hardware security byte space and is summarized in figure 27: set fps and map hardware byte (fcon = 0x0c) save and disable the interrupts. load dptr at address 0000h. load accumulator register with the data to load. execute the movx @dptr, a instruction. launch the programming by writing the data sequence 54h followed by a4h in fcon register (only from fm1). the end of the programming indicated by the fbusy flag cleared. restore the interrupts. flash spaces programming save and disable it ea = 0 launch programming fcon = 5xh fcon = axh end programming restore it column latches loading see figure 25 fbusy cleared? clear mode fcon = 00h
50 AT89C51AC3 4383b?8051?01/05 figure 27. hardware programming procedure reset the column latches an automatic reset of the column latches is performed after a successful flash write sequence. user can also reset the column latches manually, for instance to reload the column latches before writing the flash. the following procedure is summarized below. save and disable the interrupts. launch the reset by writing the data sequence 56h followed by a6h in fcon register (only from fm1). restore the interrupts. error reports flash programming sequence errors when a wrong sequence is detected, the seqerr bit in fsta register is set. possible wrong sequence are : mov fcon, 5xh instruction not immediately followed by a mov fcon, ax instruction. a write flash sequence is launched while no data were loaded in the column latches the seqerr bit can be cleared by software by hardware when a correct programming sequence is completed when multiple pages are written into the flash, the user should check fsta for errors after each write page sequences, not only at the end of the multiple write pages. flash spaces programming save and disable it ea = 0 launch programming fcon = 54h fcon = a4h end programming restoreit fbusy cleared? clear mode fcon = 00h data load dptr = 00h acc = data exec: movx @dptr, a fcon = 0ch save and disable it ea = 0 end loading restore it
51 AT89C51AC3 4383b?8051?01/05 power down request before entering in power down (set bit pd in pcon register) the user should check that no write sequence is in progress (check busy=0), then check that the column latches are reset (fload=0 in fsta register. launch a reset column latches to clear fload if necessary. reading the flash spaces user the following procedure is used to read the user space: read one byte in accumulator by executing movc a,@a+dptr with a+dptr=read@. note: fcon is supposed to be reset when not needed. extra row the following procedure is used to read the extra row space and is summarized in figure 28: map the extra row space by writing 02h in fcon register. read one byte in accumulator by executing movc a,@a+dptr with a = 0 and dptr = ff80h to ffffh. clear fcon to unmap the extra row. hardware security byte the following procedure is used to read the hardware security space and is summarized in figure 28: map the hardware security space by writing 04h in fcon register. read the byte in accumulator by executing movc a,@a+dptr with a = 0 and dptr = 0000h. figure 28. clear fcon to unmap the hardware security byte.reading procedure flash protection from parallel programming the three lock bits in hardware security byte (see "in-system programming" section) are programmed according to table 17 provide different level of protection for the on- chip code and data located in fm0 and fm1. the only way to write this bits are the parallel mode. they are set by default to level 4 flash spaces reading flash spaces mapping fcon= 00000xx0b data read dptr= address acc= 0 exec: movc a, @a+dptr clear mode fcon = 00h
52 AT89C51AC3 4383b?8051?01/05 table 17. program lock bit program lock bits u: unprogrammed p: programmed warning: security level 2 and 3 should only be programmed after flash and core verification. program lock bits protection description security level lb0 lb1 lb2 1 u u u no program lock features enabled. 2puu movc instruction executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further parallel programming of the flash is disabled. isp and software programming with api are still allowed. writing eeprom data from external parallel programmer is disabled but still allowed from internal code execution. 3upu same as 2, also verify through parallel programming interface is disabled. writing and reading eeprom data from external parallel programmer is disabled but still allowed from internal code execution.. 4 u u p same as 3, also exte rnal execution is disabled
53 AT89C51AC3 4383b?8051?01/05 operation cross memory access space addressable in read and write are: ram eram (expanded ram access by movx) xram (external ram) eeprom data fm0 ( user flash ) hardware byte xrow boot flash flash column latch the table below provide the different kind of memory which can be accessed from differ- ent code location. note: 1. rww: read while write table 18. cross memory access action ram xram eram boot flash fm0 e2 data hardware byte xrow boot flash read ok ok ok ok - write - ok (1) ok (1) ok (1) ok (1) fm0 read ok ok ok ok - write - ok (idle) ok (1) -ok external memory ea = 0 or code roll over read - - ok - - write - - ok (1) --
54 AT89C51AC3 4383b?8051?01/05 sharing instructions table 19. instructions shared note: by cl : using column latch table 20. read movx a, @dptr table 21. write movx @dptr,a action ram xram eram eeprom data boot flash fm0 hardware byte xrow read mov movx movx movc movc movc movc write mov movx movx - by cl by cl by cl eee bit in eecon register fps in fcon register enboot ea xram eram eeprom data flash column latch 00xxok 01xxok 10xx ok 11xxok eee bit in eecon register fps bit in fcon register enboot ea xram eram eeprom data flash column latch 00xxok 01x 1ok 0ok 10xx ok 11x 1ok 0ok
55 AT89C51AC3 4383b?8051?01/05 table 22. read movc a, @dptr code execution fcon register enboot dptr fm1 fm0 xrow hardware byte external code fmod1 fmod0 fps from fm0 00x 0 0000h to ffffh ok 1 0000h to f7ff ok f800h to ffffh do not use this configuration 01x x 0000 to 007fh see (1) ok 10x x x ok 11x 0 000h to ffffh ok 1 0000h to f7ff ok f800h to ffffh do not use this configuration from fm1 (enboot =1 00 0 1 0000h to f7ff ok f800h to ffffh ok 0x na 1 1x ok 0x na 01x 1 0000h to 007h see (2) ok 0na 10x 1 x ok 0na 11x 1 000h to ffffh ok 0na external code : ea=0 or code roll over x0x x x ok 1. for dptr higher than 007fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007fh 2. for dptr higher than 007fh only lowest 7 bits are decoded, thus the behavior is the same as for addresses from 0000h to 007fh
56 AT89C51AC3 4383b?8051?01/05 in-system programming (isp) with the implementation of the user space (fm0) and the boot space (fm1) in flash technology the AT89C51AC3 allows the system engineer the development of applica- tions with a very high level of flexibility. this flexibility is based on the possibility to alter the customer program at any stages of a product?s life: before assembly the 1st personalization of the product by programming in the fm0 and if needed also a customized boot loader in the fm1. atmel provide also a standard uart boot loader by default. after assembling on the pcb in its final embedded position by serial mode via the uart. this in-system programming (isp) allows code modification over the total lifetime of the product. besides the default boot loader atmel provide to the customer also all the needed appli- cation-programming-interfaces (api) which are needed for the isp. the api are located also in the boot memory. this allow the customer to have a full use of the 64-kbyte user memory. flash programming and erasure there are three methods of programming the flash memory: the atmel bootloader located in fm1 is activated by the application. low level api routines (located in fm1)will be used to program fm0. the interface used for serial downloading to fm0 is the uart. api can be called also by the user?s bootloader located in fm0 at [sbv]00h. a further method exists in activating the atmel boot loader by hardware activation. the fm0 can be programmed also by the parallel mode using a programmer. figure 29. flash memory mapping boot process software boot process example many algorithms can be used for the software boot process. before describing them, the description of the different flags and bytes is given below: f800h ffffh 64k bytes flash memory 2k bytes iap bootloader fm0 fm1 custom boot loader [sbv]00h ffffh fm1 mapped between f800h and ffff h when api called 0000h
57 AT89C51AC3 4383b?8051?01/05 boot loader jump bit (bljb): - this bit indicates if on reset the user wants to jump to this application at address @0000h on fm0 or execute the boot loader at address @f800h on fm1. - bljb = 0 on parts delivered with bootloader programmed. - to read or modify this bit, the apis are used. boot vector address (sbv): - this byte contains the msb of the user boot loader address in fm0. - the default value of sbv is ffh (no user boot loader in fm0). - to read or modify this byte, the apis are used. extra byte (eb) and boot status byte (bsb): - these bytes are reserved for customer use. - to read or modify these bytes, the apis are used. hardware boot process at the falling edge of reset, the bit enboot in auxr1 register is initialized with the value of boot loader jump bit (bljb). further at the falling edge of reset if the following conditions (called hardware condi- tion) are detected: psen low, ea high, ale high (or not connected). ? after hardware condition the fcon register is initialized with the value 00h and the pc is initialized with f800h (fm1). the hardware condition makes the bootloader to be executed, whatever bljb value is. if no hardware condition is detected, the fcon register is initialized with the value f0h. check of the bljb value. if bit bljb = 1: user application in fm0 will be started at @0000h (standard reset). if bit bljb = 0: boot loader will be started at @f800h in fm1. note: 1. as psen is an output port in normal operating mode (running user applications or bootloader applications) after reset it is recommended to release psen after the fall- ing edge of reset is signaled. the hardware conditions are sampled at reset signal falling edge, thus they can be released at any time when reset input is low. 2. to ensure correct microcontroller startup, the psen pin should not be tied to ground during power-on.
58 AT89C51AC3 4383b?8051?01/05 figure 30. hardware boot process algorithm application programming interface several application program interface (api) calls are available for use by an application program to permit selective erasing and programming of flash pages. all calls are made by functions. all these apis are describe in an documentation: "in-system programing: flash library for AT89C51AC3" available on the atmel web site. xrow bytes table 23. xrow mapping reset hardware condition? bljb = = 0 ? bit enboot in auxr1 registe r is initialized with bljb. hardware software enboot = 1 pc = f800h enboot = 1 pc = f800h fcon = 00h fcon = f0h boot loader in fm1 enboot = 0 pc = 0000h yes yes no no application in fm0 description default value address copy of the manufacturer code 58h 30h copy of the device id#1: family code d7h 31h copy of the device id#2: memories size and type ffh 60h copy of the device id#3: name and revision feh 61h
59 AT89C51AC3 4383b?8051?01/05 hardware security byte table 24. hardware security byte default value after erasing chip: ffh notes: 1. only the 4 msb bits can be accessed by software. 2. the 4 lsb bits can only be accessed by parallel mode. 76543210 x2b bljb - - - lb2 lb1 lb0 bit number bit mnemonic description 7x2b x2 bit set this bit to start in standard mode clear this bit to start in x2 mode. 6bljb boot loader jumpbit - 1: to start the user?s application on next reset (@0000h) located in fm0, - 0: to start the boot loader(@f800h) located in fm1. 5-3 - reserved the value read from these bits are indeterminate. 2-0 lb2:0 lock bits
60 AT89C51AC3 4383b?8051?01/05 serial i/o port the AT89C51AC3 i/o serial port is compatible with the i/o serial port in the 80c52. it provides both synchronous and asynchronous communication modes. it operates as a universal asynchronous receiver and transmitter (uart) in three full-duplex modes (modes 1, 2 and 3). asynchronous transmission and reception can occur simultaneously and at different baud rates serial i/o port includes the following enhancements: framing error detection automatic address recognition figure 31. serial i/o port block diagram framing error detection framing bit error detection is provided for the three asynchronous modes. to enable the framing bit error detection feature, set smod0 bit in pcon register. figure 32. framing error block diagram when this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. an invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two cpus. if a valid stop bit is not found, the framing error bit (fe) in scon register bit is set. the software may examine the fe bit after each reception to check for data errors. once set, only software or a reset clears the fe bit. subsequently received frames with valid stop bits cannot clear the fe bit. when the fe feature is enabled, ri rises on the stop bit instead of the last data bit (see figure 33. and figure 34.). write sbuf ri ti sbuf transmitter sbuf receiver ib bus mode 0 transmit receive shift register load sbuf read sbuf scon reg interrupt request serial port txd rxd ri ti rb8 tb8 ren sm2 sm1 sm0/fe idl pd gf0 gf1 pof - smod0 smod to uart framing error control sm0 to uart mode control set fe bit if stop bit is 0 (framing error)
61 AT89C51AC3 4383b?8051?01/05 figure 33. uart timing in mode 1 figure 34. uart timing in modes 2 and 3 automatic address recognition the automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (sm2 bit in scon register is set). implemented in the hardware, automatic address recognition enhances the multiproces- sor communication feature by allowing the serial port to examine the address of each incoming command frame. only when the serial port recognizes its own address will the receiver set the ri bit in the scon register to generate an interrupt. this ensures that the cpu is not interrupted by command frames addressed to other devices. if necessary, you can enable the automatic address recognition feature in mode 1. in this configuration, the stop bit takes the place of the ninth data bit. bit ri is set only when the received command frame address matches the device?s address and is terminated by a valid stop bit. to support automatic address recognition, a device is identified by a given address and a broadcast address. note: the multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting sm2 bit in scon register in mode 0 has no effect). data byte ri smod0=x stop bit start bit rxd d7 d6 d5 d4 d3 d2 d1 d0 fe smod0=1 ri smod0=0 data byte ninth bit stop bit start bit rxd d8 d7 d6 d5 d4 d3 d2 d1 d0 ri smod0=1 fe smod0=1
62 AT89C51AC3 4383b?8051?01/05 given address each device has an individual address that is specified in the saddr register; the saden register is a mask byte that contains don?t-care bits (defined by zeros) to form the device?s given address. the don?t-care bits provide the flexibility to address one or more slaves at a time. the following example illustrates how a given address is formed. to address a device by its individual address, the saden mask byte must be 1111 1111b . for example: saddr0101 0110b saden 1111 1100b given0101 01xxb here is an example of how to use given addresses to address different slaves: slave a:saddr1111 0001b saden 1111 1010b given1111 0x0xb slave b:saddr1111 0011b saden 1111 1001b given1111 0xx1b slave c:saddr1111 0011b saden 1111 1101b given1111 00x1b the saden byte is selected so that each slave may be addressed separately. for slave a, bit 0 (the lsb) is a don?t-care bit; for slaves b and c, bit 0 is a 1. to com- municate with slave a only, the master must send an address where bit 0 is clear (e.g. 1111 0000b ). for slave a, bit 1 is a 0; for slaves b and c, bit 1 is a don?t care bit. to communicate with slaves a and b, but not slave c, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b ). to communicate with slaves a, b and c, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b ). broadcast address a broadcast address is formed from the logical or of the saddr and saden registers with zeros defined as don?t-care bits, e.g.: saddr0101 0110b saden1111 1100b saddr or saden 1111 111xb the use of don?t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is ffh. the following is an example of using broadcast addresses: slave a:saddr1111 0001b saden 1111 1010b given1111 1x11b, slave b:saddr1111 0011b saden 1111 1001b given1111 1x11b, slave c:saddr=1111 0010b saden 1111 1101b given1111 1111b
63 AT89C51AC3 4383b?8051?01/05 for slaves a and b, bit 2 is a don?t care bit; for slave c, bit 2 is set. to communicate with all of the slaves, the master must send an address ffh. to communicate with slaves a and b, but not slave c, the master can send and address fbh. registers table 25. scon register scon (s:98h) serial control register reset value = 0000 0000b bit addressable 76543210 fe/sm0 sm1 sm2 ren tb8 rb8 ti ri bit number bit mnemonic description 7fe framing error bit (smod0=1 ) clear to reset the error state, not cleared by a valid stop bit. set by hardware when an invalid stop bit is detected. sm0 serial port mode bit 0 (smod0=0) refer to sm1 for serial port mode selection. 6sm1 serial port mode bit 1 sm0 sm1 mode baud rate 0 0 shift register f xtal /12 (or f xtal /6 in mode x2) 0 1 8-bit uart variable 1 0 9-bit uart f xtal /64 or f xtal /32 1 1 9-bit uart variable 5sm2 serial port mode 2 bit/multiprocessor communication enable bit clear to disable multiprocessor communication feature. set to enable multiprocessor communication feature in mode 2 and 3. 4ren reception enable bit clear to disable serial reception. set to enable serial reception. 3tb8 transmitter bit 8/ninth bit to transmit in modes 2 and 3 clear to transmit a logic 0 in the 9th bit. set to transmit a logic 1 in the 9th bit. 2rb8 receiver bit 8/ninth bit received in modes 2 and 3 cleared by hardware if 9th bit received is a logic 0. set by hardware if 9th bit received is a logic 1. 1ti transmit interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0ri receive interrupt flag clear to acknowledge interrupt. set by hardware at the end of the 8th bit time in mode 0, see figure 33. and figure 34. in the other modes.
64 AT89C51AC3 4383b?8051?01/05 table 26. saden register saden (s:b9h) slave address mask register reset value = 0000 0000b not bit addressable table 27. saddr register saddr (s:a9h) slave address register reset value = 0000 0000b not bit addressable table 28. sbuf register sbuf (s:99h) serial data buffer reset value = 0000 0000b not bit addressable 76543210 ???????? bit number bit mnemonic description 7-0 mask data for slave individual address 76543210 ???????? bit number bit mnemonic description 7-0 slave individual address 76543210 ???????? bit number bit mnemonic description 7-0 data sent/received by serial i/o port
65 AT89C51AC3 4383b?8051?01/05 table 29. pcon register pcon (s:87h) power control register reset value = 00x1 0000b not bit addressable 76543210 smod1 smod0 ? pof gf1 gf0 pd idl bit number bit mnemonic description 7smod1 serial port mode bit 1 set to select double baud rate in mode 1, 2 or 3. 6smod0 serial port mode bit 0 clear to select sm0 bit in scon register. set to select fe bit in scon register. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4pof power-off flag clear to recognize next reset type. set by hardware when vcc rises from 0 to its nominal voltage. can also be set by software. 3gf1 general-purpose flag cleared by user fo r general-purpose usage. set by user for general-purpose usage. 2gf0 general-purpose flag cleared by user fo r general-purpose usage. set by user for general-purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit clear by hardware when interrupt or reset occurs. set to enter idle mode.
66 AT89C51AC3 4383b?8051?01/05 timers/counters the AT89C51AC3 implements two general-purpose, 16-bit timers/counters. such are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or an event counter. when operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each timer/counter are described in the following sections. timer/counter operations a basic operation is timer registers thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in tcon register (see figure 30) turns the timer on by allowing the selected input to increment tlx. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer regis- ters can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, otherwise the behav- ior of the timer/counter is unpredictable. the c/tx# control bit selects timer operation or counter operation by selecting the divided-down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, otherwise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e. f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the timer register counts the negative transitions on the tx external input pin. the external input is sampled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition, the maximum count rate is f per /12, i.e. f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full peripheral cycle. timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 35 to figure 38 show the logical configuration of each mode. timer 0 is controlled by the four lower bits of tmod register (see figure 31) and bits 0, 1, 4 and 5 of tcon register (see figure 30). tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and mode of operation (m10 and m00). tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an inter- rupt request. it is important to stop timer/counter before changing mode.
67 AT89C51AC3 4383b?8051?01/05 mode 0 (13-bit timer) mode 0 configures timer 0 as an 13-bit timer which is set up as an 8-bit timer (th0 register) with a modulo 32 prescaler implemented with the lower five bits of tl0 register (see figure 35). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 35. timer/counter x (x = 0 or 1) in mode 0 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit ti mer with th0 and tl0 registers connected in cascade (see figure 36). the selected input increments tl0 register. figure 36. timer/counter x (x = 0 or 1) in mode 1 ftx clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrup t reques t c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx see the ?clock? section trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see the ?clock? section
68 AT89C51AC3 4383b?8051?01/05 mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit timer (tl0 register) that automatically reloads from th0 register (see figure 37). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 37. timer/counter x (x = 0 or 1) in mode 2 mode 3 (two 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers (see figure 38). this mode is provided for applications requiring an additional 8- bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod reg- ister, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f per /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of timer 1 is restricted when timer 0 is in mode 3. figure 38. timer/counter 0 in mode 3: two 8-bit counters trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrup t reques t c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx ftx clock 6 see the ?clock? section tr0 tcon.4 tf0 tcon.5 int0# 0 1 gate0 tmod.3 overflow timer 0 interrup t reques t c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrup t reques t t0 ftx clock 6 ftx clock 6 see the ?clock? section
69 AT89C51AC3 4383b?8051?01/05 timer 1 timer 1 is identical to timer 0 excepted for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: timer 1 functions as either a timer or event counter in three modes of operation. figure 35 to figure 37 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. timer 1 is controlled by the four high-order bits of tmod register (see figure 31) and bits 2, 3, 6 and 7 of tcon register (see figure 30). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr1 allows external pin int1# to control timer operation. timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. it is important to stop timer/counter before changing mode. mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 35). the upper 3 bits of tl1 register are ignored. prescaler overflow incre- ments th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit ti mer with th1 and tl1 registers connected in cascade (see figure 36). the selected input increments tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 register on overflow (see figure 37). tl1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not available i.e. when timer 0 is in mode 3.
70 AT89C51AC3 4383b?8051?01/05 interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cleared when vectoring to the timer interrupt routine. interrupts are enabled by setting etx bit in ien0 register. this assumes interrupts are globally enabled by setting ea bit in ien0 register. figure 39. timer interrupt system registers table 30. tcon register tcon (s:88h) timer/counter control register reset value = 0000 0000b tf0 tcon.5 et0 ien0.1 timer 0 interrupt request tf1 tcon.7 et1 ien0.3 timer 1 interrupt request 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external in terrupt is detected on int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active (edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external in terrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active (edge triggered) for external interrupt 0.
71 AT89C51AC3 4383b?8051?01/05 table 31. tmod register tmod (s:89h) timer/counter mode control register reset value = 0000 0000b 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1) (1) 1 1 mode 3: timer 1 halted. retains count 1. reloaded from th1 at overflow. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0) (2) 1 1 mode 3: tl0 is an 8-bit timer/counter th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 2. reloaded from th0 at overflow. 0 m00
72 AT89C51AC3 4383b?8051?01/05 table 32. th0 register th0 (s:8ch) timer 0 high byte register reset value = 0000 0000b table 33. tl0 register tl0 (s:8ah) timer 0 low byte register reset value = 0000 0000b table 34. th1 register th1 (s:8dh) timer 1 high byte register reset value = 0000 0000b 76543210 ???????? bit number bit mnemonic description 7:0 high byte of timer 0. 76543210 ???????? bit number bit mnemonic description 7:0 low byte of timer 0. 76543210 ???????? bit number bit mnemonic description 7:0 high byte of timer 1.
73 AT89C51AC3 4383b?8051?01/05 table 35. tl1 register tl1 (s:8bh) timer 1 low byte register reset value = 0000 0000b 76543210 ???????? bit number bit mnemonic description 7:0 low byte of timer 1.
74 AT89C51AC3 4383b?8051?01/05 timer 2 the AT89C51AC3 timer 2 is compatible with timer 2 in the 80c52. it is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, th2 and tl2 that are cascade- connected. it is controlled by t2con register (see table ) and t2mod register (see table 38). timer 2 operation is similar to timer 0 and timer 1. c/t2 selects f t2 clock /6 (timer operation) or external pin t2 (counter operation) as timer clock. setting tr2 allows tl2 to be incremented by the selected input. timer 2 includes the following enhancements: auto-reload mode (up or down counter) programmable clock-output auto-reload mode the auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto- matic reload. this feature is controlled by the dcen bit in t2mod register (see table 38). setting the dcen bit enables ti mer 2 to count up or down as shown in figure 40. in this mode the t2ex pin controls the counting direction. when t2ex is high, timer 2 counts up. timer overflow occurs at ffffh which sets the tf2 flag and generates an interrupt request. the overflow also causes the 16-bit value in rcap2h and rcap2l registers to be loaded into the timer registers th2 and tl2. when t2ex is low, timer 2 counts down. timer underflow occurs when the count in the timer registers th2 and tl2 equals the value stored in rcap2h and rcap2l registers. the underflow sets tf2 flag and reloads ffffh into the timer registers. the exf2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. exf2 does not generate an interrup t. this bit can be used to provide 17-bit resolution. figure 40. auto-reload mode up/down counter (down counting reload value) tf2 t2 exf2 th2 (8-bit) tl2 ( 8-bit) rcap2h (8-bit) rcap2l (8-bit) ffh (8-bit) ffh ( 8-bit) toggle (up counting reload value) timer 2 interrupt :6 t2conreg t2conreg t2ex: 1=up 2=down 0 1 ct/2 t2con.1 tr2 t2con.2 ft2 clock see section ?clock?
75 AT89C51AC3 4383b?8051?01/05 programmable clock- output in clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (see figure 41). the input clock increments tl2 at frequency f osc /2. the timer repeatedly counts to overflow from a loaded value. at overflow, the contents of rcap2h and rcap2l registers are loaded into th2 and tl2. in this mode, timer 2 overflows do not generate interrupts. the formula gives the clock-out frequency depending on the system oscillator frequency and the value in the rcap2h and rcap2l registers: for a 16 mhz system clock in x1 mode, timer 2 has a programmable frequency range of 61 hz (f osc /2 16) to 4 mhz (f osc /4). the generated clock signal is brought out to t2 pin (p1.0). timer 2 is programmed for the clock-out mode as follows: set t2oe bit in t2mod register. clear c/t2 bit in t2con register. determine the 16-bit reload value from the formula and enter it in rcap2h/rcap2l registers. enter a 16-bit initial value in timer registers th2/tl2. it can be the same as the reload value or different depending on the application. to start the timer, set tr2 run control bit in t2con register. it is possible to use timer 2 as a baud rate generator and a clock generator simulta- neously. for this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the rcap2h and rcap2l registers. figure 41. clock-out mode clock outfrequency ? ft 2 clock 4 65536 rcap 2 h ? rcap 2 l ? () ---------------------------------------------------------------------------------------- - = exen2 exf2 overflow t2ex th2 (8-bit) tl2 (8-bit) timer 2 rcap2h (8-bit) rcap2l (8-bit) t2oe t2con reg t2con reg t2mod reg interrupt tr2 t2con.2 ft2 clock t2 q d toggle q
76 AT89C51AC3 4383b?8051?01/05 registers table 36. t2con register t2con (s:c8h) timer 2 control register reset value = 0000 0000b bit addressable 76543210 tf2 exf2 rclk tclk exen2 tr2 c/t2# cp/rl2# bit number bit mnemonic description 7tf2 timer 2 overflow flag tf2 is not set if rclk=1 or tclk = 1. must be cleared by software. set by hardware on timer 2 overflow. 6exf2 timer 2 external flag set when a capture or a reload is caused by a negative transition on t2ex pin if exen2=1. set to cause the cpu to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. must be cleared by software. 5 rclk receive clock bit clear to use timer 1 overflow as receiv e clock for serial port in mode 1 or 3. set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4tclk transmit clock bit clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3exen2 timer 2 external enable bit clear to ignore events on t2ex pin for timer 2 operation. set to cause a capture or reload when a negative transition on t2ex pin is detected, if timer 2 is not used to clock the serial port. 2tr2 timer 2 run control bit clear to turn off timer 2. set to turn on timer 2. 1c/t2# timer/counter 2 select bit clear for timer operation (input from internal clock system: f osc ). set for counter operation (input from t2 input pin). 0 cp/rl2# timer 2 capture/reload bit if rclk=1 or tclk=1, cp/rl2# is ignored and timer is forced to auto-reload on timer 2 overflow. clear to auto-reload on timer 2 overflows or negative transitions on t2ex pin if exen2=1. set to capture on negative transitions on t2ex pin if exen2=1.
77 AT89C51AC3 4383b?8051?01/05 table 37. t2mod register t2mod (s:c9h) timer 2 mode control register reset value = xxxx xx00b not bit addressable table 38. th2 register th2 (s:cdh) timer 2 high byte register reset value = 0000 0000b not bit addressable 76543210 ------t2oedcen bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1t2oe timer 2 output enable bit clear to program p1.0/t2 as clock input or i/o port. set to program p1.0/t2 as clock output. 0 dcen down counter enable bit clear to disable timer 2 as up/down counter. set to enable timer 2 as up/down counter. 76543210 -------- bit number bit mnemonic description 7-0 high byte of timer 2.
78 AT89C51AC3 4383b?8051?01/05 table 39. tl2 register tl2 (s:cch) timer 2 low byte register reset value = 0000 0000b not bit addressable table 40. rcap2h register rcap2h (s:cbh) timer 2 reload/capture high byte register reset value = 0000 0000b not bit addressable table 41. rcap2l register rcap2l (s:ca h ) t imer 2 r e load/capture low byte register reset value = 0000 0000b not bit addressable 76543210 -------- bit number bit mnemonic description 7-0 low byte of timer 2. 76543210 -------- bit number bit mnemonic description 7-0 high byte of timer 2 reload/capture. 76543210 -------- bit number bit mnemonic description 7-0 low byte of timer 2 reload/capture.
79 AT89C51AC3 4383b?8051?01/05 watchdog timer AT89C51AC3 contains a powerful progr ammable hardware watchdog timer (wdt) that automatically resets the chip if it software fails to reset the wdt before the selected time interval has elapsed. it permits large time-out ranking from 16ms to 2s @fosc = 12mhz in x1 mode. this wdt consists of a 14-bit counter plus a 7-bit programmable counter, a watchdog timer reset register (wdtrst) and a watchdog timer programming (wdtprg) regis- ter. when exiting reset, the wdt is -by default- disable. to enable the wdt, the user has to write the sequence 1eh and e1h into wdtrst register no instruction in between. when the watchdog timer is enabled, it will incre- ment every machine cycle while the oscillator is running and there is no way to disable the wdt except through reset (either hardware reset or wdt overflow reset). when wdt overflows, it will generate an output reset pulse at the rst pin. the reset pulse duration is 96xt osc , where t osc =1/f osc . to make the best use of the wdt, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a wdt reset note: when the watchdog is enable it is impossible to change its period. figure 42. watchdog timer 6 ps cpu and peripheral clock fwd clock wdtprg reset decoder control wdtrst wr enable 14-bit counter 7-bit counter outputs reset - - - - - 2 1 0 fwd clock
80 AT89C51AC3 4383b?8051?01/05 watchdog programming the three lower bits (s0, s1, s2) located into wdtprg register permit to program the wdt duration. table 42. machine cycle count to compute wd time-out, the following formula is applied: note: svalue represents the decimal value of (s2 s1 s0) the following table outlines the time-out value for fosc xtal = 12 mhz in x1 mode table 43. time-out computation s2 s1 s0 machine cycle count 000 2 14 - 1 001 2 15 - 1 010 2 16 - 1 011 2 17 - 1 100 2 18 - 1 101 2 19 - 1 110 2 20 - 1 111 2 21 - 1 s2 s1 s0 fosc = 12 mhz fosc = 16 mhz fosc = 20 mhz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s ftime out f wd 12 2 14 2 svalue () 1 ? () ---------------------------------------------------------------- - = ?
81 AT89C51AC3 4383b?8051?01/05 watchdog timer during power-down mode and idle in power-down mode the oscillator stops, which means the wdt also stops. while in power-down mode, the user does not need to service the wdt. there are 2 methods of exiting power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering power-down mode. when power-down is exited with hardware reset, the watchdog is disabled. exiting power-down with an interrupt is sig- nificantly different. the interrupt shall be held low long enough for the oscillator to stabilize. when the interrupt is brought high, the interrupt is serviced. to prevent the wdt from resetting the device while the interrupt pin is held low, the wdt is not started until the interrupt is pulled high. it is suggested that the wdt be reset during the inter- rupt service for the interrupt used to exit power-down. to ensure that the wdt does not overflow within a few states of exiting powerdown, it is best to reset the wdt just before entering powerdown. in the idle mode, the oscillator continues to run. to prevent the wdt from resetting AT89C51AC3 while in idle mode, the user should always set up a timer that will periodi- cally exit idle, service the wdt, and re-enter idle mode. register table 44. wdtprg register wdtprg (s:a7h) watchdog timer duration programming register reset value = xxxx x000b 76543210 ?????s2s1s0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2s2 watchdog timer duration selection bit 2 work in conjunction with bit 1 and bit 0. 1s1 watchdog timer duration selection bit 1 work in conjunction with bit 2 and bit 0. 0s0 watchdog timer duration selection bit 0 work in conjunction with bit 1 and bit 2.
82 AT89C51AC3 4383b?8051?01/05 table 45. wdtrst register wdtrst (s:a6h write only) watchdog timer enable register reset value = 1111 1111b note: the wdrst register is used to reset/enable the wdt by writing 1eh then e1h in sequence without instruction between these two sequences. 76543210 ???????? bit number bit mnemonic description 7 - watchdog control value
83 AT89C51AC3 4383b?8051?01/05 serial port interface (spi) the serial peripheral interface module (spi) allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: full-duplex, three-wire synchronous transfers master or slave operation six programmable master clock rates in master mode serial clock with programmable polarity and phase master mode fault error flag with mcu interrupt capability signal description figure 43 shows a typical spi bus configuration using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices. figure 43. spi master/slaves interconnection the master device selects the individual slave devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected betw een the master device and a slave device. the mosi line is used to transfer data in series from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected betw een the slave device and a master device. the miso line is used to transfer data in series from the slave to the master. therefore, it is an output signal from the slave, and an input signal to the master. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data transmission both in and out of the devices through their mosi and miso lines. it is driven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. it is obvious that only one master (ss high level) can drive the network. the master may select each slave device by software through port pins (figure 44). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. slave 1 miso mosi sck ss miso mosi sck ss port 0 1 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss vdd master
84 AT89C51AC3 4383b?8051?01/05 in a master configuration, the ss line can be used in conjunction with the modf flag in the spi status register (spscr) to preven t multiple masters from driving mosi and sck (see error conditions). a high level on the ss pin puts the miso line of a slave spi in a high-impedance state. the ss pin could be used as a general-purpose if the following conditions are met: the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin could be pulled low. therefore, the modf flag in the spscr will never be set (1) . the device is configured as a slave with cpha and ssdis control bits set (2) . this kind of configuration can happen when the system includes one master and one slave only. therefore, the device should always be selected and there is no reason that the master uses the ss pin to select the communicating slave device. note: 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha =?0? because in this mode, the ss is used to start the transmission. baud rate in master mode, the baud rate can be selected from a baud rate generator which is con- trolled by three bits in the spcon register: spr2, spr1 and spr0.the master clock is selected from one of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. table 46 gives the different clock rates selected by spr2:spr1:spr0. in slave mode, the maximum baud rate allowed on the sck input is limited to f sys /4 table 46. spi master baud rate selection spr2 spr1 spr0 clock rate baud rate divisor (bd) 0 0 0 don?t use no brg 001 f clk periph /4 4 010 f clk periph /8 8 011 f clk periph /16 16 100 f clk periph /32 32 101 f clk periph /64 64 110 f clk periph /128 128 1 1 1 don?t use no brg
85 AT89C51AC3 4383b?8051?01/05 functional description figure 44 shows a detailed structure of the spi module. figure 44. spi module block diagram operating modes the serial peripheral interface can be configured in one of the two modes: master mode or slave mode. the configuration and initia lization of the spi module is made through two registers: the serial peripheral control register (spcon) the serial peripheral status and control register (spscr) once the spi is configured, the data exchange is made using: the serial peripheral data register (spdat) during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock line (sck) synchronizes shifting and sam- pling on the two serial data lines (mosi and miso). a slave select line (ss ) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic spi interrupt 8-bit bus 1-bit signal ss fclk receive data register spdat spi control transmit data register -modf spif ovr spte uartm spteie modfie spscr spen mstr spr2 ssdis cpol cpha spr1 spr0 spcon request periph
86 AT89C51AC3 4383b?8051?01/05 when the master device transmits data to the slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 45). figure 45. full-duplex master-slave interconnection master mode the spi operates in master mode when the master bit, mstr (1) , in the spcon register is set. only one master spi device can initiate transmissions. software begins the trans- mission from a master spi module by writing to the serial peripheral data register (spdat). if the shift register is empty, the byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the serial peripheral transfer data flag, spif, in spscr becomes set. at the same time that spif becomes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spscr) with the spif bit set, and then reading the spdat. slave mode the spi operates in slave mode when the master bit, mstr (2) , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss , of the slave device must be set to?0?. ss must remain low until the transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the master spi module. after a byte enters the shift register, it is immediately trans- ferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (3) . a slave spi must complete the write to the spdat (shift reg- ister) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data already in the shift register from the previous transmission. transmission formats software can select any of four combinations of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (4) ) and the clock phase (cpha 4 ). cpol defines the default sck line level in idle state. it has no significant effect on the transmission format. cpha defines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 46 and figure 47). the clock phase and polarity should be identical for the master spi device and the com- municating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss vdd ss ss slave mcu 1. the spi module should be configured as a master before it is enabled (spen set). also, the master spi should be configured before the slave spi. 2. the spi module should be configured as a slave before it is enabled (spen set). 3. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits, the spi should be disabled (spen =?0?).
87 AT89C51AC3 4383b?8051?01/05 figure 46. data transmission format (cpha = 0) figure 47. data transmission format (cpha = 1) figure 48. cpha/ss timing as shown in figure 46, the first sck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. the ss pin must be toggled high and then low between each byte transmitted (figure 48). figure 47 shows an spi transmission in which cpha is ?1?. in this case, the master begins driving its mosi pin on the first sck edge. therefore, the slave uses the first sck edge as a start transmission signal. the ss pin can remain low between transmis- sions (figure 48). this format may be preferred in systems having only one master and only one slave driving the miso data line. queuing transmission for an spi configured in master or slave mode, a queued data byte must be transmit- ted/received immediately after the previous transmission has completed. msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 2 45678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0)
88 AT89C51AC3 4383b?8051?01/05 when a transmission is in progress a new data can be queued and sent as soon as transmission has been completed. so it is possible to transmit bytes without latency, useful in some applications. the spte bit in spscr is set as long as the transmission buffer is free. it means that the user application can write spdat with the data to be transmitted until the spte becomes cleared. figure 49 shows a queuing transmission in master mode. once the byte 1 is ready, it is immediately sent on the bus. meanwhile an other byte is prepared (and the spte is cleared), it will be sent at the end of the current transmission. the next data must be ready before the end of the current transmission. figure 49. queuing transmission in master mode in slave mode it is almost the same except it is the external master that start the transmission. also, in slave mode, if no new data is ready, the last value received will be the next data byte transmitted. msb b6 b5 b4 b3 b2 b1 lsb mosi sck msb b6 b5 b4 b3 b2 b1 lsb byte 1 under transmission msb b6 b5 b4 b3 b2 b1 lsb msb b6 b5 b4 b3 b2 b1 lsb miso data byte 1 byte 2 byte 3 spte byte 2 under transmission
89 AT89C51AC3 4383b?8051?01/05 error conditions the following flags in the spscr register indicate the spi error conditions: mode fault error (modf) mode fault error in master mode spi indicate s that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. mode fault detection in master mode: modf is set to warn that there may be a multi-master conflict for system control. in this case, the spi system is affected in the following ways: ? an spi receiver/error cpu interrupt request is generated ? the spen bit in spcon is cleared. this disables the spi ? the mstr bit in spcon is cleared clearing the modf bit is accomplished by a read of spscr register with modf bit set, followed by a write to the spcon register. spen control bit may be restored to its orig- inal set state after the modf bit has been cleared. figure 50. mode fault conditions in master mode (cpha =?1?/cpol =?0?) note: when ss is discarded (ss disabled) it is not possible to detect a modf error in master mode because the spi is internally unselected and the ss pin is a general purpose i/o. mode fault detection in slave mode in slave mode, the modf error is detected when ss goes high during a transmission. a transmission begins when ss goes low and ends once the incoming sck goes back to its idle level following the shift of the eighteen data bit. a modf error occurs if a slave is selected (ss is low) and later unselected (ss is high) even if no sck is sent to that slave. at any time, a ?1? on the ss pin of a slave spi puts the miso pin in a high impedance state and internal state counter is cleared. also, the slave spi ignores all incoming sck clocks, even if it was already in the middle of a transmission. a new transmission will be performed as soon as ss pin returns low. sck ss (master) 1 2 3 sck cycle # 0 0 ss (slave) (from master) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 z 1 0 0 z 1 spi enable modf detected mosi miso (from master) (from slave) b5
90 AT89C51AC3 4383b?8051?01/05 figure 51. mode fault conditions in slave mode note: when ss is discarded (ss disabled) it is not possible to detect a modf error in slave mode because the spi is internally selected. also the ss pin becomes a general pur- pose i/o. overrun condition this error mean that the speed is not adapted for the running application: an overrun condition occurs when a byte has been received whereas the previous one has not been read by the application yet. the last byte (which generate the overrun error) does not overwrite the unread data so that it can still be read. therefore, an overrun error always indicates the loss of data. interrupts three spi status flags can generate a cpu interrupt requests: table 47. spi interrupts serial peripheral data transfer flag, spif: this bit is set by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt request only when spteie is disabled. mode fault flag, modf: this bit is set to indicate that the level on the ss is inconsistent with the mode of the spi (in both master and slave modes). serial peripheral transmit register empty flag, spte: this bit is set when the transmit buffer is empty (other data can be loaded is spdat). spte bit generates transmitter cpu interrupt request only when spteie is enabled. note: while using spte interruption for ?burst mode? transfers (spteie=?1?), the user software application should take care to clear spteie, during the last but one data reception (to be able to generate an interrupt on spif flag at the end of the last data reception). sck 1 2 3 sck cycle # 0 ss (slave) (from master) modf detected b6 msb b6 msb 0 z 1 0 z 1 0 z 1 0 z 1 0 modf detected mosi miso (from master) (from slave) msb b5 b4 4 flag request spif (spi data transfer) spi transmitter interrupt request modf (mode fault) spi mode-fault interrupt request spte (transmit register empty) spi trans mit register empty interrupt request
91 AT89C51AC3 4383b?8051?01/05 figure 52. spi interrupt requests generation registers three registers in the spi module provide control, status and data storage functions. these registers are describe in the following paragraphs. serial peripheral control register (spcon) the serial peripheral control register does the following: selects one of the master clock rates configure the spi module as master or slave selects serial clock polarity and phase enables the spi module frees the ss pin for a general-purpose table 48 describes this register and explains the use of each bit table 48. spcon register spcon - serial peripheral control register (0d4h) spi cpu interrupt request spif spteie spte modf modfie 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic description 7 spr2 serial peripheral rate 2 bit with spr1 and spr0 define the clock rate (see bits spr1 and spr0 for detail). 6spen serial peripheral enable cleared to disable the spi interface (internal reset of the spi). set to enable the spi interface. 5 ssdis ss disable cleared to enable ss in both master and slave modes. set to disable ss in both master and slave modes. in slave mode, this bit has no effect if cpha =?0?. when ssdis is set, no modf interrupt request is generated . 4mstr serial peripheral master cleared to configure the spi as a slave. set to configure the spi as a master.
92 AT89C51AC3 4383b?8051?01/05 reset value = 0001 0100b not bit addressable serial peripheral status register and control (spscr) the serial peripheral status register contains flags to signal the following conditions: data transfer complete write collision inconsistent logic level on ss pin (mode fault error) table 49. spscr register spscr - serial peripheral status and control register (0d5h) 3cpol clock polarity cleared to have the sck set to ?0? in idle state. set to have the sck set to ?1? in idle state. 2cpha clock phase cleared to have the data sampled when the sck leaves the idle state (see cpol). set to have the data sampled when the sck returns to idle state (see cpol). 1 spr1 spr2 spr1 spr0 serial peripheral rate 0 0 0 invalid 00 1 f clk periph /4 01 0 f clk periph /8 01 1f clk periph /16 10 0f clk periph /32 10 1f clk periph /64 11 0f clk periph /128 1 1 1 invalid 0 spr0 bit number bit mnemonic description 76543210 spif - ovr modf spte uartm spteie modfie bit number bit mnemonic description 7spif serial peripheral data transfer flag cleared by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. this bit is cleared when reading or writing spdata after reading spscr. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5ovr overrun error flag - set by hardware when a byte is receiv ed whereas spif is set (the previous received data is not overwritten). - cleared by hardware when reading spscr
93 AT89C51AC3 4383b?8051?01/05 reset value = 00x0 xxxxb not bit addressable 4modf mode fault - set by hardware to indicate that the ss pin is in inappropriate logic level (in both master and slave modes). - cleared by hardware when reading spscr when modf error occurred: - in slave mode: spi interface ignores all transmitted data while ss remains high. a new transmission is perform as soon as ss returns low. - in master mode: spi interface is disabled (spen=0, see description for spen bit in spcon register). 3 spte serial peripheral transmit register empty - set by hardware when transmit register is empty (if needed, spdat can be loaded with another data). - cleared by hardware when transmit regist er is full (no more data should be loaded in spdat). 2uartm serial peripheral uart mode set and cleared by software: - clear: normal mode, data are transmitted msb first (default) - set: uart mode, data are transmitted lsb first. 1spteie interrupt enable for spte set and cleared by software: - set to enable spte interrupt generation (when spte goes high, an interrupt is generated). - clear to disable spte interrupt generation caution: when spteie is set no interrupt generation occurred when spif flag goes high. to enable spif interrupt again, spteie should be cleared. 0modfie interrupt enable for modf set and cleared by software: - set to enable modf interrupt generation - clear to disable modf interrupt generation bit number bit mnemonic description
94 AT89C51AC3 4383b?8051?01/05 programmable counter array (pca) the pca provides more timing capabilities with less cpu intervention than the standard timer/counters. its advantages include reduced software overhead and improved accu- racy. the pca consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules. its clock input can be programmed to count any of the following signals: pca clock frequency/6 (see ?clock? section) pca clock frequency/2 timer 0 overflow external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: rising and/or falling edge capture, software timer, high-speed output, pulse width modulator. module 4 can also be programmed as a watchdog timer. see the "pca watchdog timer" section. when the compare/capture modules are programmed in capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. all five modules plus the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/os. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. pca timer the pca timer is a common time base for all five modules (see figure 53). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr (see table 8) and can be programmed to run at: 1/6 the pca clock frequency. 1/2 the pca clock frequency. the timer 0 overflow. the input on the eci pin (p1.2). pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1 16-bit module 2 p1.5/cex2 16-bit module 3 p1.6/cex3 16-bit module 4 p1.7/cex4
95 AT89C51AC3 4383b?8051?01/05 figure 53. pca timer/counter the cmod register includes three additional bits associated with the pca. the cidl bit which allows the pca to stop during idle mode. the wdte bit which enables or disables the watchdog function on module 4. the ecf bit which when set causes an interrupt and the pca overflow flag cf in ccon register to be set when the pca timer overflows. the ccon register contains the run control bit for the pca and the flags for the pca timer and each module. the cr bit must be set to run the pca. the pca is shut off by clearing this bit. the cf bit is set when the pca counter overflows and an interrupt will be generated if the ecf bit in cmod register is set. the cf bit can only be cleared by software. the ccf0:4 bits are the flags for the modules (ccf0 for module0...) and are set by hardware when either a match or a capture occurs. these flags also can be cleared by software. pca modules each one of the five compare/capture modules has six possible functions. it can perform: 16-bit capture, positive-edge triggered 16-bit capture, negative-edge triggered 16-bit capture, both positive and negative-edge triggered 16-bit software timer 16-bit high speed output 8-bit pulse width modulator. in addition module 4 can be used as a watchdog timer. cidl cps1 cps0 ecf it ch cl 16 bit up counter to pca modules fpca/6 fpca/2 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow
96 AT89C51AC3 4383b?8051?01/05 each module in the pca has a special function register associated with it (ccapm0 for module 0 ...). the ccapm0:4 registers contain the bits that control the mode that each module will operate in. the eccf bit enables the ccf flag in the ccon register to generate an interrupt when a match or compare occurs in the associated module. the pwm bit enables the pulse width modulation mode. the tog bit when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module?s capture/compare register. the match bit mat when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module?s capture/compare register. the two bits capn and capp in ccapmn register determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled. the bit ecom in ccapm register when set enables the comparator function. pca interrupt figure 54. pca interrupt system pca capture mode to use one of the pca modules in capture mode either one or both of the ccapm bits capn and capp for that module must be se t. the external cex input for the module (on port 1) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module?s capture reg- isters (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. cf cr ccon ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 pca timer/counter eccfn ccapmn.0 to interrup t ea ien0.7 ec ien0.6 ecf cmod.0
97 AT89C51AC3 4383b?8051?01/05 figure 55. pca capture mode 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module?s capture registers and when a ma tch occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set. figure 56. pca 16-bit software timer and high speed output mode cexn n = 0, 4 pca counter ch (8bits) cl (8bits) ccapnh ccapnl ccfn ccon pca interrup t reques t - 0cappn capnn 000 eccfn 7 ccapmn register (n = 0, 4) 0 ccapnl (8 bits) ccapnh (8 bits) - ecomn0 0 matn togn0 eccfn 70 ccapmn register (n = 0, 4) ch (8 bits) cl (8 bits) 16-bit comparator match enable ccfn ccon reg pca interrupt request cexn compare/capture module pca counter ?0? ?1? reset write to ccapnl write to ccapnh for software timer mode, set ecomn and matn. for high speed output mode, set ecomn, matn and togn. toggle
98 AT89C51AC3 4383b?8051?01/05 high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module?s capture registers. to activate this mode the tog, mat, and ecom bits in the module?s ccapmn sfr must be set. figure 57. pca high speed output mode pulse width modulator mode all the pca modules can be used as pwm outputs. the output frequency depends on the source for the pca timer. all the modules will have the same output frequency because they all share the pca timer. the duty cycle of each module is independently variable using the module?s capture register ccapln. when the value of the pca cl sfr is less than the value in the module?s ccapln sfr the output will be low, when it is equal to or greater than it, the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows the pwm to be updated with- out glitches. the pwm and ecom bits in the module?s ccapmn register must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer ?1? ?0? write to ccapnl reset write to ccapnh
99 AT89C51AC3 4383b?8051?01/05 figure 58. pca pwm mode pca watchdog timer an on-board watchdog timer is available wi th the pca to improve system reliability without increasing chip count. watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. module 4 is the only pca module that can be programmed as a watchdog. however, this module can still be used for other modes if the watchdog is not needed. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal reset will be generated. this will not cause the rst pin to be driven high. to hold off the reset, the user has three options: periodically change the compare value so it will never match the pca timer, periodically change the pca timer value so it will never match the compare values, or disable the watchdog by clearing the wdte bit before a match occurs and then re- enable it. the first two options are more reliable because the watchdog timer is never disabled as in the third option. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. if other pca modules are being used the second option not recommended either. remember, the pca timer is the time base for all modules; changing the time base for other modules would not be a good idea. thus, in most appli- cations the first solution is the best option. cl rolls over from ffh to 00h loads ccapnh contents into ccapnl ccapnl ccapnh 8-bit comparator cl (8 bits) ?0? ?1? cl < ccapnl cl > = ccapnl cex pwmn ccapmn.1 ecomn ccapmn.6
100 AT89C51AC3 4383b?8051?01/05 pca registers table 50. cmod register cmod (s:d9h) pca counter mode register reset value = 00xx x000b 76543210 cidl wdte - - - cps1 cps0 ecf bit number bit mnemonic description 7cidl pca counter idle control bit clear to let the pca run during idle mode. set to stop the pca when idle mode is invoked. 6wdte watchdog timer enable clear to disable watchdog timer function on pca module 4, set to enable it. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2-1 cps1:0 ewc count pulse select bits cps1 cps0 clock source 0 0 internal clock, fpca/6 0 1 internal clock, fpca/2 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max. rate = fpca/4) 0ecf enable pca counter overflow interrupt bit clear to disable cf bit in ccon register to generate an interrupt. set to enable cf bit in ccon register to generate an interrupt.
101 AT89C51AC3 4383b?8051?01/05 table 51. ccon register ccon (s:d8h) pca counter control register reset value = 00x0 0000b 76543210 cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 bit number bit mnemonic description 7cf pca timer/counter overflow flag set by hardware when the pca timer/count er rolls over. this generates a pca interrupt request if the ecf bit in cmod register is set. must be cleared by software. 6cr pca timer/counter run control bit clear to turn the pca timer/counter off. set to turn the pca timer/counter on. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4 ccf4 pca module 4 compare/capture flag set by hardware when a match or c apture occurs. this generates a pca interrupt request if the eccf 4 bi t in ccapm 4 register is set. must be cleared by software. 3 ccf3 pca module 3 compare/capture flag set by hardware when a match or c apture occurs. this generates a pca interrupt request if the eccf 3 bi t in ccapm 3 register is set. must be cleared by software. 2 ccf2 pca module 2 compare/capture flag set by hardware when a match or c apture occurs. this generates a pca interrupt request if the eccf 2 bi t in ccapm 2 register is set. must be cleared by software. 1 ccf1 pca module 1 compare/capture flag set by hardware when a match or c apture occurs. this generates a pca interrupt request if the eccf 1 bi t in ccapm 1 register is set. must be cleared by software. 0 ccf0 pca module 0 compare/capture flag set by hardware when a match or c apture occurs. this generates a pca interrupt request if the eccf 0 bi t in ccapm 0 register is set. must be cleared by software.
102 AT89C51AC3 4383b?8051?01/05 table 52. ccapnh registers ccap0h (s:fah) ccap1h (s:fbh) ccap2h (s:fch) ccap3h (s:fdh) ccap4h (s:feh) pca high byte compare/capture module n register (n=0..4) reset value = 0000 0000b table 53. ccapnl registers ccap0l (s:eah) ccap1l (s:ebh) ccap2l (s:ech) ccap3l (s:edh) ccap4l (s:eeh) pca low byte compare/capture module n register (n=0..4) reset value = 0000 0000b 76543210 ccapnh 7 ccapnh 6 ccapnh 5 ccapnh 4 ccapnh 3 ccapnh 2 ccapnh 1 ccapnh 0 bit number bit mnemonic description 7:0 ccapnh 7:0 high byte of ewc-pca comparison or capture values 76543210 ccapnl 7 ccapnl 6 ccapnl 5 ccapnl 4 ccapnl 3 ccapnl 2 ccapnl 1 ccapnl 0 bit number bit mnemonic description 7:0 ccapnl 7:0 low byte of ewc-pca comparison or capture values
103 AT89C51AC3 4383b?8051?01/05 table 54. ccapmn registers ccapm0 (s:dah) ccapm1 (s:dbh) ccapm2 (s:dch) ccapm3 (s:ddh) ccapm4 (s:deh) pca compare/capture module n mode registers (n=0..4) reset value = x000 0000b 76543210 - ecomn cappn capnn matn togn pwmn eccfn bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6ecomn enable compare mode module x bit clear to disable the compare function. set to enable the compare function. the compare function is used to implem ent the software timer, the high-speed output, the pulse width modulator (pwm) and the watchdog timer (wdt). 5 cappn capture mode (positive) module x bit clear to disable the capture function triggered by a positive edge on cexx pin. set to enable the capture function trig gered by a positive edge on cexx pin 4capnn capture mode (negative) module x bit clear to disable the capture function triggered by a negative edge on cexx pin. set to enable the capture function triggered by a negative edge on cexx pin. 3matn match module x bit set when a match of the pca counter with the compare/capture register sets ccfx bit in ccon register, flagging an interrupt. 2 togn toggle module x bit the toggle mode is configured by setting ecomx, matx and togx bits. set when a match of the pca counter with the compare/capture register toggles the cexx pin. 1pwmn pulse width modulation module x mode bit set to configure the module x as an 8-bit pulse width modulator with output waveform on cexx pin. 0eccfn enable ccfx interrupt bit clear to disable ccfx bit in ccon regi ster to generate an interrupt request. set to enable ccfx bit in ccon register to generate an interrupt request.
104 AT89C51AC3 4383b?8051?01/05 table 55. ch register ch (s:f9h) pca counter register high value reset value = 0000 00000b table 56. cl register cl (s:e9h) pca counter register low value reset value = 0000 00000b 76543210 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 bit number bit mnemonic description 7:0 ch 7:0 high byte of timer/counter 76543210 cl 7 cl 6 cl 5 cl 4 cl 3 cl 2 cl 1 cl 0 bit number bit mnemonic description 7:0 cl0 7:0 low byte of timer/counter
105 AT89C51AC3 4383b?8051?01/05 analog-to-digital converter (adc) this section describes the on-chip 10 bit analog-to-digital converter of the AT89C51AC3. eight adc channels are available for sampling of the external sources an0 to an7. an analog multiplexer allows the single adc converter to select one from the 8 adc channels as adc input voltage (a dcin). adcin is converted by the 10-bit cascaded potentiometric adc. two kinds of conversion are available: - standard conversion (8 bits). - precision conversion (10 bits). for the precision conversion, set bit psid le in adcon register and start conversion. the device is in a pseudo-idle mode, the cpu does not run but the peripherals are always running. this mode allows digital noise to be as low as possible, to ensure high precision conversion. for this mode it is necessary to work with end of conversion interrupt, which is the only way to wake the device up. if another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. features 8 channels with multiplexed inputs 10-bit cascaded potentiometric adc conversion time 16 micro-seconds (typ.) zero error (offset) 2 lsb max positive external reference voltage range (vref) 2.4 to 3.0volt (typ.) adcin range 0 to 3volt integral non-linearity typical 1 lsb, max. 2 lsb differential non-linearity typical 0.5 lsb, max. 1 lsb conversion complete flag or conversion complete interrupt selectable adc clock adc port1 i/o functions port 1 pins are general i/o that are shared with the adc channels. the channel select bit in adcf register define which adc channel/port1 pin will be used as adcin. the remaining adc channels/port1 pins can be used as general-purpose i/o or as the alter- nate function that is available. a conversion launched on a channel which are not selected on adcf register will not have any effect.
106 AT89C51AC3 4383b?8051?01/05 figure 59. adc description figure 60 shows the timing diagram of a complete conversion. for simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. for adc characteristics and timing parameters refer to the section ?ac characteristics? of the AT89C51AC3 datasheet. figure 60. timing diagram note: tsetup min = 4 us tconv=11 clock adc = 1sample and hold + 10 bit conversion the user must ensure that 4 us minimum time between setting aden and the start of the first conversion. an0/p1.0 an1/p1.1 an2/p1.2 an3/p1.3 an4/p1.4 an5/p1.5 an6/p1.6 an7/p1.7 000 001 010 011 100 101 110 111 sch2 adcon.2 sch0 adcon.0 sch1 adcon.1 adc clock aden adcon.5 adsst adcon.3 adeoc adcon.4 adc interrupt request eadc ien1.1 control avss sample and hold addh varef r/2r dac vagnd 8 10 + - addl 2 sar adcin aden adsst adeoc t setup t conv clk
107 AT89C51AC3 4383b?8051?01/05 adc converter operation a start of single a/d conversion is triggered by setting bit adsst (adcon.3). after completion of the a/d conversion, the adsst bit is cleared by hardware. the end-of-conversion flag adeoc (adcon.4) is set when the value of conversion is available in addh and addl, it must be cleared by software. if the bit eadc (ien1.1) is set, an interrupt occur when flag adeoc is set (see figure 62). clear this flag for re- arming the interrupt. the bits sch0 to sch2 in adcon register are used for the analog input channel selection. table 57. selected analog input voltage conversion when the adcin is equals to varef the adc converts the signal to 3ffh (full scale). if the input voltage equals vagnd, the adc converts it to 000h. input voltage between varef and vagnd are a straight-line linear conversion. all other voltages will result in 3ffh if greater than varef and 000h if less than vagnd. note that adcin should not exceed varef absolute maximum range! (see section ?ac-dc?) clock selection the adc clock is the same as cpu. the maximum clock frequency is defined in the dc parmeters for a/d converter. a pres- caler is featured (adcclk) to generate the adc clock from the oscillator frequency. f adc = fcpu clock/ (4 (or 2 in x2 mode)* prs ) if prs > 0 then f adc = f periph / 2 x prs if prs = 0 then f adc = f periph / 64 sch2 sch1 sch0 selected analog input 000an0 001an1 010an2 011an3 100an4 101an5 110an6 111an7
108 AT89C51AC3 4383b?8051?01/05 figure 61. a/d converter clock adc standby mode when the adc is not used, it is possible to set it in standby mode by clearing bit aden in adcon register. in this mode its power dissipation is about 1 w. it adc management an interrupt end-of-conversion will occurs wh en the bit adeoc is activated and the bit eadc is set. for re-arming the interrupt the bit adeoc must be cleared by software. figure 62. adc interrupt structure routines examples 1. configure p1.2 and p1.3 in adc channels // configure channel p1.2 and p1.3 for adc adcf = 0ch // enable the adc adcon = 20h 2. start a standard conversion // the variable "channel" contai ns the channel to convert // the variable "value_conv erted" is an unsigned int // clear the field sch[2:0] adcon and = f8h // select channel adcon | = channel // start conversion in standard mode adcon | = 08h // wait flag end of conversion while((adcon and 01h)! = 01h) // clear the end of conversion flag adcon and = efh // read the value value_converted = (addh << 2)+(addl) 3. start a precision conversion (need interrupt adc) // the variable "channel" contai ns the channel to convert // enable adc prescaler adclk a/d converter adc clock cpu clock cpu core clock symbol 2 adeoc adcon.2 eadc ien1.1 adci
109 AT89C51AC3 4383b?8051?01/05 eadc = 1 // clear the field sch[2:0] adcon and = f8h // select the channel adcon | = channel // start conversion in precision mode adcon | = 48h note: to enable the adc interrupt: ea = 1
110 AT89C51AC3 4383b?8051?01/05 registers table 58. adcf register adcf (s:f6h) adc configuration reset value =0000 0000b table 59. adcon register adcon (s:f3h) adc control register reset value =x000 0000b 76543210 ch 7 ch 6 ch 5 ch 4 ch 3 ch 2 ch 1 ch 0 bit number bit mnemonic description 7-0 ch 0:7 channel configuration set to use p1.x as adc input. clear to use p1.x as standart i/o port. 76543210 - psidle aden adeoc adsst sch2 sch1 sch0 bit number bit mnemonic description 7- 6 psidle pseudo idle mode (best precision) set to put in idle mode during conversion clear to convert without idle mode. 5aden enable/standby mode set to enable adc clear for standby mode (power dissipation 1 uw). 4adeoc end of conversion set by hardware when adc result is ready to be read. this flag can generate an interrupt. must be cleared by software. 3 adsst start and status set to start an a/d conversion. cleared by hardware after completion of the conversion 2-0 sch2:0 selection of channel to convert see table 57
111 AT89C51AC3 4383b?8051?01/05 table 60. adclk register adclk (s:f2h) adc clock prescaler reset value = xxx0 0000b note: 1. in x1 mode: for prs > 0 f adc = fxtal 4xprs for prs = 0 f adc = fxtal 128 in x2 mode: for prs > 0 f adc = fxtal 2xprs for prs = 0 f adc = fxtal 64 table 61. addh register addh (s:f5h read only) adc data high byte register reset value = 00h table 62. addl register addl (s:f4h read only) adc data low byte register 76543210 - - - prs 4prs 3prs 2prs 1prs 0 bit number bit mnemonic description 7-5 - reserved the value read from these bits are indeterminate. do not set these bits. 4-0 prs4:0 clock prescaler see note (1) 76543210 adat 9 adat 8 adat 7 adat 6 adat 5 adat 4 adat 3 adat 2 bit number bit mnemonic description 7-0 adat9:2 adc result bits 9-2 76543210 ------adat 1adat 0
112 AT89C51AC3 4383b?8051?01/05 reset value = 00h bit number bit mnemonic description 7-2 - reserved the value read from these bits are indeterminate. do not set these bits. 1-0 adat1:0 adc result bits 1-0
113 AT89C51AC3 4383b?8051?01/05 interrupt system introduction the micro-controller has a total of 9 interrupt vectors: two external interrupts (int0 and int1 ), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a pca, a timer overrun interrupt and an adc. these interrupts are shown below. figure 63. interrupt control system ex0 ien0.0 00 01 10 11 external interrupt 0 int0# ea ien0.7 ex1 ien0.2 external interrupt 1 int1# et0 ien0.1 timer 0 ec ien0.6 pca et1 ien0.3 timer 1 es ien0.4 uart eadc ien1.1 a to d converter interrupt enable lowest priority interrupts highest priority enable 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 priority interrup ts ain1:0 iph/l timer 2 00 01 10 11 et2 ien0.5 txd rxd cex0:5 00 01 10 11 espi ien1.3 spi controller
114 AT89C51AC3 4383b?8051?01/05 each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register. this register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt priority registers. the table below shows the bit values and priority levels associated with each combination. table 63. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. if two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence, see table 64. table 64. interrupt priority within level iph.x ipl.x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest) interrupt name interrupt address vector priority number external interrupt (int0) 0003h 1 timer0 (tf0) 000bh 2 external interrupt (int1) 0013h 3 timer1 (tf1) 001bh 4 pca (cf or ccfn) 0033h 5 uart (ri or ti) 0023h 6 timer2 (tf2) 002bh 7 adc (adci) 0043h 8 spi interrupt 0053h 9
115 AT89C51AC3 4383b?8051?01/05 registers table 65. ien0 register ien0 (s:a8h) interrupt enable register reset value = 0000 0000b bit addressable 76543210 ea ec et2 es et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is indivi dually enabled or disabled by setting or clearing its interrupt enable bit. 6ec pca interrupt enable clear to disable the pca interrupt. set to enable the pca interrupt. 5et2 timer 2 overflow interrupt enable bit clear to disable timer 2 overflow interrupt. set to enable timer 2 overflow interrupt. 4es serial port enable bit clear to disable serial port interrupt. set to enable serial port interrupt. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2ex1 external interrupt 1 enable bit clear to disable external interrupt 1. set to enable external interrupt 1. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0.
116 AT89C51AC3 4383b?8051?01/05 table 66. ien1 register ien1 (s:e8h) interrupt enable register reset value = xxxx 0x0xb bit addressable 76543210 ----espi-eadc- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3espi spi interrupt enable bit clear to disable the spi interrupt. set to enable the spi interrupt. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1 eadc adc interrupt enable bit clear to disable the adc interrupt. set to enable the adc interrupt. 0- reserved the value read from this bit is indeterminate. do not set this bit.
117 AT89C51AC3 4383b?8051?01/05 table 67. ipl0 register ipl0 (s:b8h) interrupt enable register reset value = x000 0000b bit addressable 76543210 - ppc pt2 ps pt1 px1 pt0 px0 bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 ppc pca interrupt priority bit refer to ppch for priority level 5pt2 timer 2 overflow interrupt priority bit refer to pt2h for priority level. 4ps serial port priority bit refer to psh for priority level. 3pt1 timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1 external interrupt 1 priority bit refer to px1h for priority level. 1pt0 timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0 external interrupt 0 priority bit refer to px0h for priority level.
118 AT89C51AC3 4383b?8051?01/05 table 68. ipl1 register ipl1 (s:f8h) interrupt priority low register 1 reset value = xxxx 0x0xb bit addressable 76543210 ----spil-p adcl - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3spil spi interrupt priority level less significant bit refer to spih for priority level. 2- reserved the value read from this bit is indeterminate. do not set this bit. 1padcl adc interrupt priority level less significant bit refer to pspih for priority level. 0- reserved the value read from this bit is indeterminate. do not set this bit.
119 AT89C51AC3 4383b?8051?01/05 table 69. ipl0 register iph0 (b7h) interrupt high priority register reset value = x000 0000b 76543210 - ppch pt2h psh pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6 ppch pca interrupt priority level most significant bit ppch ppc priority level 0 0 lowest 0 1 1 0 1 1 highest priority 5pt2h timer 2 overflow interrupt high priority bit pt2h pt2 priority level 0 0 lowest 0 1 1 0 1 1 highest 4 psh serial port high priority bit psh ps priority level 0 0 lowest 0 1 1 0 1 1 highest 3pt1h timer 1 overflow interrupt high priority bit pt1h pt1 priority level 0 0 lowest 0 1 1 0 1 1 highest 2px1h external interrupt 1 high priority bit px1h px1 priority level 0 0 lowest 0 1 1 0 1 1 highest 1pt0h timer 0 overflow interrupt high priority bit pt0h pt0 priority level 0 0 lowest 0 1 1 0 1 1 highest 0px0h external interrupt 0 high priority bit px0h px0 priority level 0 0 lowest 0 1 1 0 1 1 highest
120 AT89C51AC3 4383b?8051?01/05 table 70. iph1 register iph1 (s:f7h) interrupt high priority register 1 reset value = xxxx 0x0xb 76543210 ----spih-p adch - bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3spih spi interrupt priority level most significant bit spih spil priority level 0 0 lowest 0 1 1 0 1 1 highest 2- reserved the value read from this bit is indeterminate. do not set this bit. 1 padch adc interrupt priority level most significant bit padch padcl priority level 0 0 lowest 0 1 1 0 1 1 highest 0- reserved the value read from this bit is indeterminate. do not set this bit.
121 AT89C51AC3 4383b?8051?01/05 electrical characteristics absolute maximum ratings dc parameters for standard voltage t a = -40 c to +85 c; v ss = 0v; v cc =2.7v to 5.5v and f = 0 to 40 mhz (both internal and external code execution) v cc =4.5v to 5.5v and f = 0 to 60 mhz (internal code execution only) ambiant temperature under bias: i = industrial ....................................................... -40 c to 85 c storage temperature .................................... -65 c to + 150 c voltage on v cc from v ss ......................................-0.5v to + 6v voltage on any pin from v ss ..................... -0.5v to v cc + 0.2v power dissipation .............................................................. 1 w table 71. dc parameters in standard voltage symbol parameter min typ (5) max unit test conditions v il input low voltage -0.5 0.2vcc - 0.1 v v ih input high voltage except xtal1, rst 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage, xtal1, rst 0.7 v cc v cc + 0.5 v v ol output low voltage, ports 1, 2, 3 and 4 (6) 0.3 0.45 1.0 v v v i ol = 100 a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) v ol1 output low voltage, port 0, ale, psen (6) 0.3 0.45 1.0 v v v i ol = 200 a (4) i ol = 3.2 ma (4) i ol = 7.0 ma (4) v oh output high voltage, ports 1, 2, 3, and 4 v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -10 a i oh = -30 a i oh = -60 a v cc = 3v to 5.5v v oh1 output high voltage, port 0, ale, psen v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v i oh = -200 a i oh = -3.2 ma i oh = -7.0 ma v cc = 5v 10% r rst rst pulldown resistor 50 100 200 k ? i il logical 0 input current ports 1, 2, 3 and 4 -50 a vin = 0.45v i li input leakage current 10 a 0.45v < vin < v cc i tl logical 1 to 0 transition current, ports 1, 2, 3 and 4 -650 a vin = 2.0v c io capacitance of i/o buffer 10 pf fc = 1 mhz t a = 25 c i pd power-down current 75 150 a3v < v cc < 5.5v (3) note: stresses at or above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. the power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package.
122 AT89C51AC3 4383b?8051?01/05 notes: 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 67.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; ea = rst = port 0 = v cc . i cc would be slightly higher if a crystal oscillator used (see figure 64.). 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; port 0 = v cc ; ea = rst = v ss (see figure 65.). 3. power-down i cc is measured with all output pins disconnected; ea = v cc , port 0 = v cc ; xtal2 nc.; rst = v ss (see fig- ure 66.). in addition, the wdt must be inactive and the pof flag must be set. 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature. 6. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum i ol per 8-bit port: port 0: 26 ma ports 1, 2, 3 and 4: 15 ma maximum total i ol for all output pins: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. figure 64. i cc test condition, active mode i cc power supply current i ccop = 0.4 frequency (mhz) + 8 i ccidle = 0.2 frequency (mhz) + 8 ma vcc = 5.5v (1)(2) table 71. dc parameters in standard voltage (continued) symbol parameter min typ (5) max unit test conditions ea v cc v cc i cc (nc) clock signal v cc all other pins are disconnected. rst xtal2 xtal1 v ss v cc p0
123 AT89C51AC3 4383b?8051?01/05 figure 65. i cc test condition, idle mode figure 66. i cc test condition, power-down mode figure 67. clock signal waveform for i cc tests in active and idle modes dc parameters for a/d converter table 72. dc parameters for ad converter in precision conversion note: 1. typicals are based on a limited number of samples and are not guaranteed. rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. clock signal rst ea xtal2 xtal1 v ss v cc v cc i cc (nc) p0 v cc all other pins are disconnected. v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns. symbol parameter min typ (1) max unit test conditions avin analog input voltage vss- 0.2 vref + 0.2 v rref resistance between vref and vss 12 16 24 k ? vref reference voltage 2.40 3.00 v cai analog input capacitance 60 pf during sampling rai analog input resistor 400 ? during sampling inl integral non linearity 1 2 lsb dnl differential non linearity 0.5 1 lsb oe offset error -2 2 lsb
124 AT89C51AC3 4383b?8051?01/05 ac parameters explanation of the ac symbols each timing symbol has 5 characters. the firs t character is always a ?t? (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the fo llowing is a list of all the characters and what they stand for. example: t avll = time for address valid to ale low. t llpl = time for ale low to psen low. t a = -40 c to +85 c; v ss = 0v; v cc = 3v to 5.5v; f = 0 to 40 mhz. (load capacitance for port 0, ale and psen = 60 pf; load capacitance for all other outputs = 60 pf.) table 73, table 76 and table 79 give the description of each ac symbols. table 74, table 78 and table 80 give for each range the ac parameter. table 75, table 78 and table 81 give the frequency derating formula of the ac parame- ter for each speed range description. to ca lculate each ac symbols: take the x value and use this value in the formula. example: t lliv and 20 mhz, standard clock. x = 30 ns t = 50 ns t cciv = 4t - x = 170 ns
125 AT89C51AC3 4383b?8051?01/05 external program memory characteristics table 73. symbol description table 74. ac parameters for a fix clock (f = 40 mhz) symbol parameter t oscillator clock period t lhll ale pulse width t av ll address valid to ale t llax address hold after ale t lliv ale to valid instruction in t llpl ale to psen t plph psen pulse width t pliv psen to valid instruction in t pxix input instruction hold after psen t pxiz input instruction float after psen t aviv address to valid instruction in t plaz psen low to address float symbol min max units t25 ns t lhll 40 ns t avll 10 ns t llax 10 ns t lliv 70 ns t llpl 15 ns t plph 55 ns t pliv 35 ns t pxix 0ns t pxiz 18 ns t aviv 85 ns t plaz 10 ns
126 AT89C51AC3 4383b?8051?01/05 table 75. ac parameters for a variable clock external program memory read cycle symbol type standard clock x2 clock x parameter units t lhll min 2 t - x t - x 10 ns t avll min t - x 0.5 t - x 15 ns t llax min t - x 0.5 t - x 15 ns t lliv max 4 t - x 2 t - x 30 ns t llpl min t - x 0.5 t - x 10 ns t plph min 3 t - x 1.5 t - x 20 ns t pliv max 3 t - x 1.5 t - x 40 ns t pxix min x x 0 ns t pxiz max t - x 0.5 t - x 7 ns t aviv max 5 t - x 2.5 t - x 40 ns t plaz max x x 10 ns t pliv tplaz ale psen port 0 port 2 a0-a7 a0-a7 instr in instr in instr in address or sfr-p2 address a8-a15 address a8-a15 12 t clcl t av iv t lhll t avll t lliv t llpl t plph t pxav t pxix t pxiz t llax
127 AT89C51AC3 4383b?8051?01/05 external data memory characteristics table 76. symbol description table 77. ac parameters for a variable clock (f=40mhz) symbol parameter t rlrh rd pulse width t wlwh wr pulse width t rldv rd to valid data in t rhdx data hold after rd t rhdz data float after rd t lldv ale to valid data in t avdv address to valid data in t llwl ale to wr or rd t avw l address to wr or rd t qvwx data valid to wr transition t qvwh data set-up to wr high t whqx data hold after wr t rlaz rd low to address float t whlh rd or wr high to ale high symbol min max units t rlrh 130 ns t wlwh 130 ns t rldv 100 ns t rhdx 0ns t rhdz 30 ns t lldv 160 ns t avdv 165 ns t llwl 50 100 ns t avwl 75 ns t qvwx 10 ns t qvwh 160 ns t whqx 15 ns t rlaz 0ns t whlh 10 40 ns
128 AT89C51AC3 4383b?8051?01/05 table 78. ac parameters for a variable clock symbol type standard clock x2 clock x parameter units t rlrh min 6 t - x 3 t - x 20 ns t wlwh min 6 t - x 3 t - x 20 ns t rldv max 5 t - x 2.5 t - x 25 ns t rhdx min x x 0 ns t rhdz max 2 t - x t - x 20 ns t lldv max 8 t - x 4t -x 40 ns t avdv max 9 t - x 4.5 t - x 60 ns t llwl min 3 t - x 1.5 t - x 25 ns t llwl max 3 t + x 1.5 t + x 25 ns t avwl min 4 t - x 2 t - x 25 ns t qvwx min t - x 0.5 t - x 15 ns t qvwh min 7 t - x 3.5 t - x 25 ns t whqx min t - x 0.5 t - x 10 ns t rlaz max x x 0 ns t whlh min t - x 0.5 t - x 15 ns t whlh max t + x 0.5 t + x 15 ns
129 AT89C51AC3 4383b?8051?01/05 external data memory write cycle external data memory read cycle serial port timing ? shift register mode table 79. symbol description (f = 40 mhz) t qvwh t llax ale psen wr port 0 port 2 a0-a7 data out address or sfr-p2 t avw l t llwl t qvwx address a8-a15 or sfr p2 t whqx t whlh t wlwh ale psen rd port 0 port 2 a0-a7 data in address or sfr-p2 t avwl t llwl t rlaz address a8-a15 or sfr p2 t rhdz t whlh t rlrh t lldv t rhdx t llax t avdv symbol parameter t xlxl serial port clock cycle time t qvhx output data set-up to clock rising edge t xhqx output data hold after clock rising edge t xhdx input data hold after clock rising edge t xhdv clock rising edge to input data valid
130 AT89C51AC3 4383b?8051?01/05 table 80. ac parameters for a fix clock (f = 40 mhz) table 81. ac parameters for a variable clock shift register timing waveforms external clock drive characteristics (xtal1) table 82. ac parameters symbol min max units t xlxl 300 ns t qvhx 200 ns t xhqx 30 ns t xhdx 0ns t xhdv 117 ns symbol type standard clock x2 clock x parameter for -m range units t xlxl min 12 t 6 t ns t qvhx min 10 t - x 5 t - x 50 ns t xhqx min 2 t - x t - x 20 ns t xhdx min x x 0 ns t xhdv max 10 t - x 5 t- x 133 ns valid valid valid valid valid valid input data valid 0123456 8 7 ale clock output data write to sbuf clear ri t xlxl t qvxh t xhqx t xhdv t xhdx set ti set ri instruction 01234567 valid symbol parameter min max units t clcl oscillator period 25 ns t chcx high time 5 ns t clcx low time 5 ns t clch rise time 5 ns t chcl fall time 5 ns t chcx /t clcx cyclic ratio in x2 mode 40 60 %
131 AT89C51AC3 4383b?8051?01/05 external clock drive waveforms ac testing input/output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t chcl t clcx t clcl t clch t chcx input/output 0.2 v cc + 0.9 0.2 v cc - 0.1 v cc -0.5v 0.45v float v oh - 0.1 v v ol + 0.1 v v load v load + 0.1 v v load - 0.1 v
132 AT89C51AC3 4383b?8051?01/05 clock waveforms valid in normal clock mode. in x2 mode xtal2 must be changed to xtal2/2. this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperature and pin loading. propaga- tion also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if progra m memory is externa l) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled
133 AT89C51AC3 4383b?8051?01/05 flash/eeprom memory table 83. timing symbol definitions table 84. memory ac timing vdd = 3v to 5.5v, ta = -40 to +85 c figure 68. flash memory ? isp waveforms figure 69. flash memory ? internal busy waveforms signals conditions s (hardware condition) psen#,ea l low rrst vvalid b fbusy flag x no longer valid symbol parameter min typ max unit t svrl input psen# valid to rst edge 50 ns t rlsx input psen# hold after rst edge 50 ns t bhbl flash/eeprom internal busy (programming) time 10 ms rst t svrl psen#1 t rlsx fbusy bit t bhbl
134 AT89C51AC3 4383b?8051?01/05 ordering information table 85. possible order entries part number boot loader temperature range package packing product marking AT89C51AC3-rltim uart industrial vqfp44 tray AT89C51AC3-im AT89C51AC3-slsim uart industrial plcc44 stick AT89C51AC3-im AT89C51AC3-rdtim uart industrial vqfp64 tray AT89C51AC3-im AT89C51AC3-s3sim uart industrial plcc52 stick AT89C51AC3-im
135 AT89C51AC3 4383b?8051?01/05 package drawing vqfp44
136 AT89C51AC3 4383b?8051?01/05 plcc44
137 AT89C51AC3 4383b?8051?01/05 vqfp64
138 AT89C51AC3 4383b?8051?01/05 plcc52
139 AT89C51AC3 4383b?8051?01/05 datasheet change log changes from 4383a 10/04 - 4383b 01/05 1. various minor corrections made throughout the document.
140 AT89C51AC3 4383b?8051?01/05
1 AT89C51AC3 4383b?8051?01/05 features................................................................................................ 1 description ........................................................................................... 1 block diagram...................................................................................... 2 pin configuration................................................................................. 3 i/o configurations................................................................................................. 7 port 1, port 3 and port 4 ....................................................................................... 7 port 0 and port 2................................................................................................... 8 read-modify-write instructions ............................................................................ 9 quasi-bidirectional port operation ..................................................................... 10 sfr mapping...................................................................................... 11 clock ................................................................................................... 15 description.......................................................................................................... 15 registers............................................................................................................. 18 data memory ...................................................................................... 20 internal space..................................................................................................... 21 external space ................................................................................................... 22 dual data pointer ............................................................................................... 24 registers............................................................................................................. 25 power monitor.................................................................................... 27 description.......................................................................................................... 27 reset ................................................................................................... 29 introduction ......................................................................................................... 29 reset input ......................................................................................................... 29 reset output........................................................................................................ 30 power management ........................................................................... 31 introduction ......................................................................................................... 31 idle mode ............................................................................................................ 31 power-down mode ............................................................................................. 31 registers............................................................................................................. 34 eeprom data memory...................................................................... 35 write data in the column latches ...................................................................... 35 programming ...................................................................................................... 35 read data........................................................................................................... 35 examples ............................................................................................................ 36 registers............................................................................................................. 37
2 AT89C51AC3 4383b?8051?01/05 program/code memory ..................................................................... 38 flash memory architecture................................................................................. 40 overview of fm0 operations .............................................................................. 44 operation cross memory access .................................................... 53 sharing instructions.......................................................................... 54 in-system programming (isp) .......................................................... 56 flash programming and erasure........................................................................ 56 boot process ...................................................................................................... 56 application programming interface..................................................................... 58 xrow bytes....................................................................................................... 58 hardware security byte ...................................................................................... 59 serial i/o port .................................................................................... 60 framing error detection .................................................................................... 60 automatic address recognition.......................................................................... 61 given address ................................................................................................... 62 broadcast address ............................................................................................ 62 registers............................................................................................................. 63 timers/counters ................................................................................ 66 timer/counter operations .................................................................................. 66 timer 0................................................................................................................ 66 timer 1................................................................................................................ 69 interrupt .............................................................................................................. 70 registers............................................................................................................. 70 timer 2 ................................................................................................ 74 auto-reload mode............................................................................................. 74 programmable clock-output .............................................................................. 75 registers............................................................................................................. 76 watchdog timer................................................................................. 79 watchdog programming ..................................................................................... 80 watchdog timer during power-down mode and idle ......................................... 81 serial port interface (spi).................................................................. 83 features.............................................................................................................. 83 signal description............................................................................................... 83 functional description ........................................................................................ 85 programmable counter array (pca) ............................................... 94 pca timer .......................................................................................................... 94 pca modules...................................................................................................... 95
3 AT89C51AC3 4383b?8051?01/05 pca interrupt ...................................................................................................... 96 pca capture mode............................................................................................. 96 16-bit software timer mode ............................................................................... 97 high speed output mode ................................................................................... 98 pulse width modulator mode.............................................................................. 98 pca watchdog timer ........................................................................................ 99 pca registers .................................................................................................. 100 analog-to-digital converter (adc)................................................. 105 features............................................................................................................ 105 adc port1 i/o functions .................................................................................. 105 adc converter operation................................................................................. 107 voltage conversion .......................................................................................... 107 clock selection ................................................................................................. 107 adc standby mode .......................................................................................... 108 it adc management ........................................................................................ 108 routines examples ........................................................................................... 108 registers........................................................................................................... 110 interrupt system .............................................................................. 113 introduction ....................................................................................................... 113 registers........................................................................................................... 115 electrical characteristics................................................................ 121 absolute maximum ratings ..............................................................................121 dc parameters for standard voltage ................................................................ 121 dc parameters for a/d converter .................................................................... 123 ac parameters ..................................................................................................124 ordering information....................................................................... 134 package drawing ............................................................................. 135 vqfp44 ............................................................................................................ 135 plcc44 ............................................................................................................ 136 vqfp64 ............................................................................................................ 137 plcc52 ............................................................................................................ 138 datasheet change log.................................................................... 139 changes from 4383a 10/04 - 4383b 01/05 ...................................................... 139
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